Service manual

Error Registers 6-13
Table 6-5 CAP Error Register (continued)
Name Bits Type
Initial
State Description
LOST_MC_ERR <24> RW1C 0 Set when an error is detected
but not logged because the
associated symptom fields
and registers are locked with
the state of an earlier error.
PIO_OVFL <23> RW1C 0 Set when a transaction that
targets this system bus to PCI
bus bridge is not serviced
because the buffers are full.
This is a symptom of setting
the PEND_NUM field in
CAP_CNTL to an incorrect
value.
Reserved <22:5> RO 0
PCI_ERR_VALID <4> RO 0 Logical OR of bits <3:0> of
this register. When set, the
PCI error address register is
locked.
PTE_INV <3> RW1C 0 Invalid page table entry on
scatter/gather access.
MAB <2> RW1C 0 PCI master state machine
detected PCI Target Abort
(likely cause: NXM) (except
Special Cycle). On reads fill
error is also returned.
SERR <1> RW1C 0 PCI target state machine
observed SERR#. CAP
asserts SERR when it is
master and detects target
abort.
PERR <0> RW1C 0 PCI master state machine
observed PERR#.