Service manual

Error Registers 6-9
6.1.3 MC Error Information Register 1
(MC_ERR1 - Offset = 840)
The high-order MC bus (system bus) address bits and error symptoms are
latched into this register when the system bus to PCI bus bridge detects an
error. If the event is a hard error, the register bits are locked. A write to clear
symptom bits in the CAP Error Register unlocks this register. When the valid
bit (MC_ERR_VALID) in the CAP Error Register is clear, the contents are
undefined.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Failing Address ADDR<39:32>
MC Command<5:0>
reserved
DEVICE_ID
1 1 1 MID
VALID
Dirty