Service manual

Error Logs 5-39
5.3.6 MCHK 630 Correctable CPU Error
The error log in Example 5-6 shows the following:
➊ CPU0 logged the error in a system with two CPUs.
➋ During a D-ref fill, the External Interface Status Register shows no error
but states that the “data source is b-cache.” (When a CPU chip does not
find data it needs to perform a task in any of its caches, it requests data
from off the chip to fill its D-cache. It performs a D-ref fill.)
➌ Both IOD CAP Error Registers logged no error.
➍ The FIL Syndrome Register has a valid ECC code for the lower half of the
data.
Machine check 630s are detected by CPUs when they either take data off the system
bus or when they access their own B-cache. In this case, the data did not come from
the system bus, otherwise bit <30> would be set in the External Interface Status
Register. CPU0 had a single-bit, ECC correctable error.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “Horse” module referred to in the error log is the
system bus to PCI bus bridge module, the B3040 module. The “Saddle” module is
the PCI motherboard, the B3050 module. The “MC” bus is the system bus.
Refer to Table 5-9 for information on decoding commands, and refer to Table 5-10
for information on node IDs.