Service manual

5-34 AlphaServer 4000/4100 Service Manual
PCI Class Code x00000600
MC-PCI Command Register x06470FB1 Module SelfTest Passed LED on
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions: Enabled
Bridge WILL NOT REQUEST 64 Bit Data Trans
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check: Enabled
MC Bus CMD/Addr Parity Check: Enabled
MC Bus NXM Check: Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 7.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE Arbitration: MC-PCI Priority Mode
Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000
IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000
Interrupt Ctrl Register x00000003 Write Device Interrupt Info
Struct:Enabled
Interrupt Request x00000000 Interrupts asserted x00000000
Interrupt Mask0 Register x00C50110
Interrupt Mask1 Register x00000000
➌
MC Error Info Register 0 xE0000000
MC Bus Trans Addr<31:4>: E0000000
MC Error Info Register 1 x000E89FD MC bus trans addr <39:32> x000000FD
MC Command is Read1-IO
CPU0 Master at Time of Error
Device ID 2 x00000002
CAP Error Register x00000000
Sys Environmental Regs x00000000
PCI Bus Trans Error Adr x00000000
MDPA Status Register x00000000 MDPA Status Register Data Not Valid
MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not
Valid
MDPB Status Register x00000000 MDPB Status Register Data Not Valid
MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not
Valid
** IOD SUBPACKET -> ** IOD 1 Register Subpacket
WHOAMI x000008BA Module Revision 2.
VCTY ASIC Rev = 0
Bcache Size = 2MB
MID 2.
GID 7.
Base Address of Bridge x000000FBE0000000
Dev Type & Rev Register x06000231 CAP Chip Revision: x00000001
HORSE Module Revision: x00000003
SADDLE Module Revision: x00000002
SADDLE Module Type: Left Hand
Internal CAP Chip Arbiter: Enabled
PCI Class Code x00000600
MC-PCI Command Register x06470FB1 Module SelfTest Passed LED on
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions: Enabled
Bridge WILL NOT REQUEST 64 Bit Data Trans
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check: Enabled
MC Bus CMD/Addr Parity Check: Enabled
MC Bus NXM Check: Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 7.