Service manual

Error Logs 5-3
Lines Protected Device
ECC Protected
System bus data lines IOD on every transaction,
CPU when using the bus
B-cache IOD on every transaction,
CPU when using the bus
Parity Protected
System bus command/address lines IOD on every transaction,
CPU when using the bus
Duplicate tag store IOD on every transaction,
CPU when using the bus
B-cache index lines CPU
PCI bus IOD
EISA bus EISA bridge
As shown in Figure 5-1 and the accompanying table, the CPU chip is isolated by
transceivers (XVER) from the data and command/address lines on the module. This
allows the CPU chip access to the duplicate tag and B-cache while the system bus is
in use. The CPU detects errors only when it is the consumer of the data. The IOD
detects errors on each system bus cycle regardless of whether it is involved in the
transaction.
System bus errors detected by the CPU may also be detected by the IOD. It is
necessary to check the IOD for errors any time there is a CPU machine check.
• If the CPU sees bad data and the IOD does not, the CPU is at fault.
• If both the CPU and the IOD see bad data on the system bus, either memory or a
secondary CPU is the cause. In such a case, the Dirty bit, bit<20>, in the IOD
MC_ERR1 Register should be set or clear. If the Dirty bit is set, the source of
the data is a CPU’s cache destined for a different CPU. If the Dirty bit is not
set, memory caused the bad data on the bus. In this case, multiple error log
entries occur and must be analyzed together to determine the cause of the error.