Technical data
7
-4
9050 Peripherals
5W2
51: Bidirectional Bus Enable:
Up - Disabled.
Down
- Enabled.
52: Internal Handshake Enable;
Up - Disabled.
Down
- Enabled.
53:
Full/Pulse Handshake Enable;
Up - Disabled.
Down
- Enabled (HP 97060A).
54
and
5S: Data Input Clock 5elect;
Both Down
- Backplane sync cycle completion.
Both
Up - Backplane sync cycle completion.
54
Up and
5S
Down - Busy to ready edge of PFLAG
(trail edge)
54
Down and
5S
Up - Ready to busy edge of PFLAG
(lead edge)
Ensure that jumpers
WI,
W2, and W3 are
in
the correct position.
It may
be
necessary to increase the delay
on
the GPIO card.
Use
the following procedure.
Two one-shots (ElS)
on
the GPIO card generate the write delay and the internal handshake
delay. The write delay one-shot provides approximately
100 nsec
for
the output data to settle.
When extra long cables are used, or when the peripheral device requires additional settling time
for
the data, the delay can
be
increased by adding a capacitor between pins 1 and 4 of the
socket at E16.
The formula for selecting the capacitor value
is:
C = (T-I00)/1.S Where: C = Added Capacitance
(in
pf)
T = Total time delay
(in
nsec)
The internal delay
one
shot provides a delay of approximately 3 usec between the assertion of
PCNTL
and
the assertion of
FLAG.
The delay can be increased by adding a capacitor between
pins
Sand
8 of the socket at E16.
The formula for selecting the capacitor value
is:
C = (T-3000)/3
Connections
Where: C = Added Capacitance
(in
pf)
T = Total time delay
(in
nsec)
Cabling information
is
in
the configuration section.