Specifications

Figure 9. Basic block diagram of the HP 9000 rp8440 Server I/O subsystem
I/O controller chips
The HP 9000 rp7440 and rp8440 Servers contain two master I/O controller chips located on the
PCI-X backplane. Each I/O controller contains 16 high-performance, 12-bit-wide links. These links
connect to 16 I/O controller chips supporting the PCI-X card slots and core I/O.
In both systems, two links—one from each master controller—are routed through the system backplane
and are dedicated to core I/O. The remaining 30 links are divided among the sixteen 64-bit PCI-X
card slots, with each slot on a dedicated PCI-X bus. This one-card-per-bus architecture leads to greater
I/O performance, better error containment, and higher availability.
Each controller chip is also directly linked to a host cell board, which means that two cell boards,
located in cell slots 0 and 1, must be purchased to access all available I/O card slots. (With one cell
board, access to half of the available slots is enabled.)
PCI-X backplane
Figures 10 and 11 show detailed views of the HP 9000 rp7440 and rp8440 Server PCI-X
backplanes. The I/O slot implementations between the two servers are almost identical—the
difference is the use of one or two slots by the HP 9000 rp7440 Server core I/O. In both figures,
note that eight of the 16 I/O card slots are supported by dual high-performance fat links. These dual-
link I/O slots provide a maximum of 2.1 GB/s of peak bandwidth for the slot. Six of the 16 I/O card
links are supported by high-performance fat links. These fat link slots provide a maximum of 1.06
GB/s of peak bandwidth for the slot. The remaining two I/O slots are single links and provide a
maximum of 530 MB/s of peak bandwidth. Aggregate I/O slot bandwidth is approximately
25 GB/s or a 4.4x increase in bandwidth compared to the sx1000 platforms.
These platform supports eight 266-MHz slots, which means that these I/O slots allows the industry’s
highest-performing PCI-X cards to run at their maximum design speed.
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