Specifications

The CC also supports DCS, an increased level of memory availability. The memory error correcting
logic reestablishes chip-spare correction after another DRAM in the same error checking and
correcting (ECC) codeword has failed. This strategy is more cost-effective than memory mirroring
methods for protecting memory. See the HP sx2000 chipset technical white paper for more
information on this feature.
Cell configurations
The HP 9000 rp7440 Server supports up to two cells. The HP 9000 rp8440 Server supports up to
four cells. With Dual-Core PA-8900 processors, each cell can be configured with up to four active
processors. When configured with PA-8900 processors, each cell can be purchased with one to four
active PA-8900 processors. A fully loaded HP 9000 rp7440 Server therefore contains eight PA-8900
processors. A fully loaded HP 9000 rp8440 Server therefore contains sixteen PA-8900 processors.
They an also be purchased in combination with inactive HP Instant Capacity (iCAP) processors.
Within the cell, CPU-to-CC peak bandwidth has been increased to 17 GB/s (13.6 GB/s sustained).
The minimum supported cell configuration is one active Dual-Core processor and 2 GB of memory per
cell board. The maximum configuration includes four active Dual-Core processors and 64 GB of
memory per cell board in the HP 9000 rp7440 Server. The HP 9000 rp8440 Server supports a
maximum of four active Dual-Core processors and 64 GB of memory per cell board. DIMM modules
are sold in sets of two, with available DIMM sizes of 1 GB, 2 GB, and 4 GB. Memory pairs of
different sizes can be mixed within a chassis and within a cell. However, for optimum memory
interleaving and performance, HP recommends that one memory size be selected, distributed evenly
across available cells, and loaded in increments of eight DIMMs.
Within a cell, the CC-to-memory peak bandwidth is 17.2 GB/s, a 2.1X improvement compared to
sx1000. Memory is accessed directly through the CC, so all memory slots are accessed, regardless of
the number of processors loaded on the cell.
Memory latency
There are two types of memory latency within the HP 9000 rp7440 Server:
• Memory latency within the cell refers to the case in which an application runs on a partition that
consists of a single cell or uses cell local memory.
• Memory latency between cells refers to the case in which the partition consists of two cells and cell
interleaved memory is used. In this case, 50% of the addresses are to memory on the same cell as
the requesting processor, and the other 50% of the addresses are to memory on the other cell.
The HP 9000 rp7440 Server average memory latency depends on the number of processors in the
partition. Assuming that memory accesses are equally distributed across all cell boards and memory
controllers within the partition, the average idle memory latency (load-to-use) is shown in the following
table.
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