Technical data

1-24
General Information
Model 743 and Model 744 VME Board Computers
The VME controller ASIC supports the following additional features:
• 16 deep by 1 byte message FIFO with interrupt on not empty
• 256 µs arbitration timer
• Ability to generate interrupts on any one of IRQ1 to IRQ7; programmable IACK status/ID.
• Automatic slot 1 detect by way of sensing VME BGIN[3] at power up.
• DMA controller with programmable bus tenure
• Independent location monitor
• IRQ1 to IRQ7 interrupt handling individually programmable.
• Programmable BR0 to BR3 levels (processor and DMA programmed separately)
• Programmable bus error timer from 10 µs to 1.28 ms
• Programmable request mode: ROR, RWD, RWD/Fair
• Reception of read-modify-write cycles (Software protocol must be enforced for processor
accesses to insure mutual exclusivity.)
• Selective generation of read-modify-write cycles
• Slot 1 arbiter programmable for RR or PRI bus arbitration
• VME64 "lock" address modifier cycles
Table 1-21 summarizes VME performance. The values shown in this table reflect raw hard-
ware speed and do not include software overhead or system overhead.
Interval Timers Three interval timers are part of the VME controller ASIC. These timers
provide interrupts on terminal count and interrupt and restart on terminal count capability.
Table 1-22 summarizes the specifications for the interval timer.
Watchdog Timer The VME controller ASIC also includes a watchdog timer used with the
HP-RT operating system.
Table 1-21 VME Performance in MB/sec
D32 MBLT
Read Write Read Write
Master 10 12 38 44
Slave 9 13 33 38
Table 1-22 Interval Timer Specifications
Resolution Drift
Timer 1 length 32 bits, cascadeable into timer 2
Timer 2 length 16 bits, cascadeable into timer 3
Timer 3 length 16 bits