Datasheet

on a read transaction.
DIMM Address/Control Bus Parity Protection provides a means to detect and protect command
and address errors.
Memory Failover uses a mirrored DIMM once a failed DIMM in a mirrored set is detected.
Memory Mirroring provides a copy of memory stored with dynamic failover in case of failure
within socket (intra-socket) memory mirroring.
The system will operate in non-hemisphere mode when mirroring is enabled.
Rank Sparring (On Line Spare) provides dynamic failover to a spare DIMM rank or spare rank pair
behind the same memory controller. Cannot be enabled concurrently with memory mirroring.
NOTE:
NOTE:NOTE:
NOTE: HP offers the rank sparing rather than DIMM sparing as rank sparing uses less spare
memory resulting in less overhead.
Failed DIMM Isolation identifies a specific failing DIMM lockstep pair thereby enabling the user to
replace only the failed DIMM pair. Identifies a single DIMM for correctable errors and DIMM pair
for uncorrectable errors.
Virtualization
VirtualizationVirtualization
Virtualization
Intel® VT-x (FlexMigration, FlexPriority, and Extended Page Tables) provides:
Platform control between the VMM and guest OSs for faster, more reliable and secure
transfers.
VM migration features that enhance flexibility for failover, load balancing, disaster recovery,
and maintenance.
Intel® VT-x Real Mode & Pause Loop Exiting (BL620c G7 Intel Xeon E7-2800/8867L models):
Real Mode allows guests to operate in real mode, removing the performance overhead and
complexity of an emulator.
Pause Loop Exiting provides detection of spin locks in guest software and helps avoid lock-
holder preemption to reduce overhead and improve performance.
Intel® VT-d (Intel® Virtualization Technology for Directed I/O) enables the VMM to assign specific
I/O devices to specific guest OSs improving security and availability.
Mezzanine options and I/O
Mezzanine options and I/OMezzanine options and I/O
Mezzanine options and I/O
Optional dual-port Fibre Channel mezzanine cards for redundant SAN connections.
Optional dual-port InfiniBand mezzanine cards for redundant high performance connections.
Four embedded Ethernet adapter ports for redundant LAN connections.
Multiple mezzanine I/O expansion slots each supported multiple data paths routed to redundant
interconnect modules.
Network Adapter Teaming (Bonding) provides network fault tolerance, transmit load balancing,
and switch-assisted load balancing.
Processor/Chipset
Processor/ChipsetProcessor/Chipset
Processor/Chipset
Processor Internal Sensors & Thermal Control protection against over-temperature conditions.
Cache parity/ECC protects cache data from accidental data corruption due to particle hits.
Machine Check Architecture (MCA) detects and captures hardware errors such as system bus,
ECC, parity, cache, other.
Enhanced MCA handling & error logging builds upon the original Machine Check Architecture to:
offers more "banks" and increased "resolution" for reporting errors that cause MCA events and 2)
sets check flags for the OS to poll.
External Bus Error Recovery (ECC) enables automatic correction from a single data bit error and
detection of double data error bits on the memory data bus.
Corrupt Data Containment tags faulty data before it is consumed (often called data poisoning) to
limit the impact to the currently running program and to greatly reduce the need to reset the
QuickSpecs
HP ProLiant BL620c Generation 7 (G7) Server Blade
HP ProLiant BL620c Generation 7 (G7) Server BladeHP ProLiant BL620c Generation 7 (G7) Server Blade
HP ProLiant BL620c Generation 7 (G7) Server Blade
Standard Features
DA - 13747 Worldwide — Version 22 — March 6, 2012 Page 12