Service manual
CPU Assembly
3-6
DMA for ECG Data
The System Gate Array receives data from the ECG Front End in serial form. When 16
bits have been received, the System Gate Array places the CPU in a HOLD state, and
generates the necessary address and control signals needed to write the data into the
System Memory (DRAM). After the data are successfully written, the HOLD state is
discontinued and the CPU resumes its processing. The System Gate Array can also deliver
interrupts to the CPU to indicate when a frame (1 msec) and/or a buffer-full (100 msec) of
data have been written into memory.
DMA for LCD Data
In the 200/200i/300pi, the System Gate Array reads 16 bits of LCD data from System
Memory (DRAM) and delivers it to the LCD for display at an approximately 8 µsec
intervals. The process of reading the 16 bits is to first place the CPU in a HOLD state, then
to generate the necessary address and control signals to read the data, then to discontinue
the HOLD state and allow the CPU to resume processing. The data are delivered one
nibble (4 bits) at a time to the LCD, after which time the HOLD cycle is repeated.
System Reset Circuitry
At a normal power on (pressing ), the CPU and most other circuits are reset to
a known initial state by the internally generated signal NRESET. This signal is created
within the System Gate Array, which is always active and operating.
Removing all power resets all circuits, including the System Gate Array, via the signal
NNEW5V. Removing all power also resets the real-time clock and date.
Watch-dog Circuitry
The watch-dog circuit will turn off the instrument within 7-8 seconds unless periodically
reset by the control software.
Real-Time Clock
The real-time clock maintains the current date and time. This clock operates off the
cardiograph battery and will run as long as the battery is installed and charged.
DRAM RAS and CAS Generation and Refresh
Refresh of the DRAM is accomplished using a CAS (Column Address Strobe) before
RAS (Row Address Strobe) technique. RAS and CAS are DRAM control signals used to
latch the desired memory address location. A refresh of one row in the DRAM occurs
approximately every 15 µsec.
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