Service manual

CPU Assembly Connectors
A-13
FEDATA Serial data from front end.
FEPWR Front end transformer drive control.
FSW_+5V Filtered switched 5 V.
GPIO0-GPIO3 General purpose I/O bits
GROUND ground.
HLDA Hold acknowledge from CPU.
INT1 Interrupt to CPU.
LAD4-LAD15 Latched CPU address bus.
nAS CPU address strobe.
nBE0, BE1 CPU byte enable — low/high.
nBLAST Indicates last byte of CPU burst transfer.
nDEN CPU data enable.
nFECLK Serial clock from front end.
infecting Serial control data to front-end.
nNEW5V Master reset to System Gate Array.
nREADY Derived from wait state generator. Terminates current bus cycle.
nRESET CPU reset.
nROMOE ROM output enable.
nXROMCS Extended ROM chip select.
ONSTBY
On/Standby signal from key.
PLOADON Signal indicating Print internal load is on.
PPWRON Signal indicating Vprint is on.
V_PRINT Printer power.
VBAT Battery voltage.
WnR Write/Read. CPU control bus signal. Distinguishes write cycles from
read cycles.
XWAIT Input to request additional CPU wait states.
Signal Definition
On-Standby