Product Drawings

SHEET FUNCTION DESCRIPTION
SHEET DESCRIPTION
1
2
3
Title Page
Top level schematic block
4
6
9
UNLESS OTHERWISE SPECIFIED:
1. THIS DRAWING IS CAD GENERATED AND MAINTAINED. CHANGES SHALL BE INCORPORATED
BY THE CURRENT DESIGN ACTIVITY.
2. PARTIAL REFERENCE DESIGNATIONS ARE SHOWN:
FOR COMPLETE DESIGNATION PREFIX WITH UNIT NUMBER, ASSEMBLY DESIGNATIONS AND
SUBASSEMBLY DESIGNATIONS PLEASE SEE BOM.
3. RESISTOR VALUES ARE GIVEN IN OHMS.
4. CAPACITOR VALUES ARE GIVEN IN MICRO FARADS.
5. NOT-INSTALLED (DNI) COMPONENTS ARE SHOWN FOR REFERENCE ONLY.
NOTES:
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11
System Block Diagram
NET NAMING CONVENTION:
ACTICE HIGH SIGNALS: SIG
ACTIVE LOW SIGNALS: SIG_B
DIFFERENTIAL PAIRS: SIG_P/SIG_N
eMMC Flash
Power Supply
Processor - DRAM & SPI interface
DRAM - Bank 1
DRAM - Bank 2
12 Board Interface - SODIMM pins 1-122
5 Processor - Clocks; debug; crypto & comms i/f
7 Processor - Boot config; eMMC & Ethernet i/f
8 Processor - Power, ground and decoupling
13 Board Interface - SODIMM pins 123-204
6. I2C ADDRESS GIVEN AS 8-BIT VALUE. BIT 0 RESERVED FOR READ/WRITE.
7. THIS SCHEMATIC USES NAMED BUS SIGNALS, ENSURE THE FOLLOWING SETTINGS ARE SET:
"SHOW RIPPER INDEXES" AND "USE FULL BUS RIPPER NAME ON RIPPER".
DxDESIGNER
SCALE:
DRAWING NO.SIZE REV
D
12
345
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7
8
A
B
C
D
HONEYWELL INTERNATIONAL INC.
A
B
C
D
12
345
6
7
8
DRAWN BY
CPO-PC200,CPO-PC400,CPO-PC400W
SOM Board
M Back
NONE
A
@PRINTORDER=1
Number
23Jun2017
HONEYWELL CONFIDENTIAL
AND PROPRIETARY
12/09/2018:13:40
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