Product Drawings
Table Of Contents
- E Sheet SOM_CONN (1)
- E Sheet 24V_Power (2)
- E Sheet LED_DRVER_RST_Button (3)
- E Sheet FRAM_RTC (4)
- E Sheet RS485 (5)
- E Sheet RS485_2 (6)
- E Sheet MMI (7)
- E Sheet 1000M_ETH (8)
- E Sheet 1000M_ETH_Power (9)
- E Sheet 100M_ETH (10)
- E Sheet ETH_CONN (11)
- E Sheet ETH_CONN2 (12)
- E Sheet USB_SD_LED_CONN (13)
- E Sheet Connector (14)
- E Sheet WD_Relay (15)
- Schematic__LED board.pdf
- Schematic__SOM board.pdf
- DDR3L_256K_X16 Sheet 1
- PROCESSOR Sheet Clock and debug
- PROCESSOR Sheet DRAM and SPI
- PROCESSOR Sheet BOOT and Interfaces
- PROCESSOR Sheet Power and decoupling
- PCD_INTERFACE Sheet SODIMM 1-122
- PCD_INTERFACE Sheet SODIMM 123-204
- PCD CPU Sheet Title (1)
- PCD CPU Sheet Block diagram (2)
- PCD CPU Sheet Top Level Schematic (3)
- DDR3L_256K_X16 Sheet 1 (9)
- DDR3L_256K_X16 Sheet 1 (10)
- EMMC_4GB_1 Sheet 1 (11)
- POWER_1 Sheet 1 (4)
- PROCESSOR Sheet Clock and debug (5)
- PROCESSOR Sheet DRAM and SPI (6)
- PROCESSOR Sheet BOOT and Interfaces (7)
- PROCESSOR Sheet Power and decoupling (8)
- PCD_INTERFACE Sheet SODIMM 1-122 (12)
- PCD_INTERFACE Sheet SODIMM 123-204 (13)
- EMMC_4GB_1 Sheet 1
- POWER_1 Sheet 1
- Schematic__USB.pdf
- Schematics_Module.pdf
GND
ID
VBUS
D+
NC
D-
DIONTWK
NC
Note: 90 ohm differential pair
Route differential pair through protection
array and test points without creating
stubs.
Place CM choke and protection
array close to USB connector.
GND
ID
VBUS
D+
NC
D-
DIONTWK
NC
Note: 90 ohm differential pair
Route differential pair through protection
array and test points without creating
stubs.
Place CM choke and protection
array close to USB connector.
USB1_DP
USB1_DN
USB2_POWER
+3V3
USB1_POWER
USB1_ID
USB1_ID
6
5
DN1
3
2
4
1
DN2
6
2
3
4
5
1
C6
100V
0.01uF
0.01uF
C7
100V
10K
R13
TP27
USB1_DN
USB1_DP
TSTPT
TP23
R14
0
USB2_POWER
USB1_POWER
USB2USB_2_DP
USB2USB_2_DN
USB2USB_2_DP
USB2USB_2_DN
USB2_DN
USB2_DP
USB2_DP
USB2_DN
0R34
0R35
0R36
0R37
R38 0
R39 0
0R40
0R41
USB_Uplink_DN
USB_Uplink_DP
USB_Uplink_DN
USB_Uplink_DP
J5
11
12
9
10
8
7
6
5
4
3
2
1
IO
IO
IO
IO
IO
IO
IO
IO
MTG
MTG
MTG
MTG
8968-A08C00RWA
EN
FLGIN
OUT
GND
ILIM
EXPPAD[GND]
PWR SW
+3V3
EN
FLGIN
OUT
GND
ILIM
EXPPAD[GND]
PWR SW
+3V3
39K
R42
0.1uF
C19
1%
63mW
R9
10K
10K
63mW
R10
1%
VCC_5V
TP19
TP20
3
4
6
5
1
2
U1
7
NCP380HMUAJAATBG
USB2_OC_B
Note: USB1 From SOM is OTG
USB2 From SOM/USB Switch are HOST only
USB2_PWR
USB2_PWR
USB2_OC_B
39K
R43
0.1uF
C20
63mW
10K
1%
R11
10K
R15
63mW
1%
VCC_5V
TP21
TP22
U6
4
6
2
7
3
1
5
NCP380HMUAJAATBG
USB1_OC_B
USB1_PWR
USB1_OC_B
USB1_PWR
10V
10%
C24
10uF
10%
10V
10uF
C25
USB2_POWER USB1_POWER
800mA
L3
BLM18HE601SN1D
Place close to connector
USB2_POWER
L4
BLM18HE601SN1D
800mA
Place close to connector
USB1_POWER
HOST USB
DEV/OTG USB
IO
IO
IO
IO
IO
MTG
MTG
MTG
MTG
MTG
MTG
3
5
1
4
2
10
11
8
9
7
P1
6
105017-0001
D+, D–, and ID pins are exact equivalent ESD clamp circuits. Any of these pins can be connected to any other D+,
D–, or ID pin if it becomes easier to route the traces from the USB connector.
TP8
TP10
HOST
OTG
C41
16V
20%
150uF
150uF
20%
16V
C42
DxDESIGNER
SCALE:
DRAWING NO.SIZE REV
D
12
345
6
7
8
A
B
C
D
HONEYWELL INTERNATIONAL INC.
A
B
C
D
12
345
6
7
8
DRAWN BY
DESIGNER
H135733 H275008
30 Sep 2018
32336513
AND PROPRIETARY
HOME & BUILDING TECHNOLOGIES
30 Sep 2018
B
30/11/2018:16:23
H135733 H275008
@PRINTORDER=2
NONE
HONEYWELL CONFIDENTIAL