User's Manual
COMPANY CONFIDENTIAL
14
3.4 Power On Sequence
PDn must remain asserted for a minimum of 1ms after VIO,SLP_CLK and XTAL_IN
are stable.
For auto reference clock detection ,the sleep clock(32.768KHz) must be used and
must be stable before PDn is de-asserted.
3.5 SDIO Host Interface Specification
Figure2 SDIO Timing Date