Hard disk drive specifications Deskstar 180 GXP 3.5 inch Ultra ATA/100 hard disk drive Models: IC35L030AVV207 IC35L060AVV207 IC35L090AVV207 IC35L120AVV207 IC35L180AVV207 Revision 4.
Hard disk drive specifications Deskstar 180 GXP 3.5 inch Ultra ATA/100 hard disk drive Models: IC35L030AVV207 IC35L060AVV207 IC35L090AVV207 IC35L120AVV207 IC35L180AVV207 Revision 4.
1st Edition (Revision 1.0) S-08K-0000-00 (18 December 2001) Preliminary 2nd Edition (Revision 2.0) S-08K-0000-00 (18 April 2002) Preliminary 3rd Edition (Revision 2.1) S-08K-0000-00 (21 June 2002) Preliminary 4rd Edition (Revision 2.2) S-08K-0000-00 (25 July 2002) Preliminary 5th Edition (Revision 2.3) S-08K-0000-01 (01 August 2002) Preliminary 6th Edition (Revision 2.5) S-08K-0000-02 (06 August 2002) Preliminary 7th Edition (Revision 3.0) S-08K-0000-03 (16 August 2002) Preliminary 8th Edition (Revision 4.
Table of contents List of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1.0 1.1 1.2 1.3 2.0 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General caution . .
.5.1 Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Power supply current (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Power supply generated ripple at drive power connector . . . . . . . . . . . . . . . . . . . . . 6.6 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.0 General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.1 Reset response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.1.1 Register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.2 Diagnostic and reset considerations . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 Execute Device Diagnostic (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Flush Cache (E7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 Flush Cache Ext (EAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Format Track (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.42.6 Self-test log data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.42.7 Error reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.43 Standby (E2h/96h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.44 Standby Immediate (E0h/94h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures Figure 1. Formatted capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. Mechanical positioning performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. Cylinder allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. Command overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 53. Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 54. Power supply current of 180 GB models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 55. Power supply current of 80 GB and 120 GB models . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 56. Power supply current of 60 GB, 40GB, and 30 GB models . . . . . . . . . . . . . . . . . . . 48 Figure 57.
Figure 108. Idle Immediate Command (E1h/95h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 109. Initialize Device Parameters Command (91h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 110. NOP Command (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 111. Read Buffer Command (E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 112.
Figure 164. SMART summary error log sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 165. Error log data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 166. Command data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 167. Error data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.0 General This document describes the specifications of the Deskstar 180GXP, an IBM 3.5-inch 7200-rpm ATA interface hard disk drive with the following model numbers: y y y y y y y IC35L030AVV207- 0 IC35L060AVV207- 0 IC35L090AVV207- 0 IC35L090AVV207- 1 IC35L120AVV207- 0 IC35L120AVV207- 1 IC35L180AVV207- 1 (30.7 GB, 2-MB buffer) (41.2 GB and 60.4 GB, 2-MB buffer) (82.3 GB, 2-MB buffer) (82.3 GB, 8-MB buffer) (123.5 GB, 2-MB buffer) (123.5 GB, 8-MB buffer) (185.
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2.0 General features y Data capacities of 30 GB - 180 GB y Spindle speeds of 7200 RPM y Fluid Dynamic Bearing motor y Enhanced IDE interface y Sector format of 512 bytes/sector y Closed-loop actuator servo y Load/Unload mechanism y Automatic Actuator lock y Interleave factor 1:1 y Seek time of 8.8 ms (30-GB, 40-GB, and 60-GB models), 8.5 ms (all other models) in Read Operation y Seek time of 8.5 ms (30-GB, 40-GB, and 60-GB models), 8.
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Part 1.
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3.0 Fixed disk subsystem description 3.1 Control Electronics The drive is electronically controlled by a microprocessor, several logic modules, digital/analog modules, and various drivers and receivers. The control electronics performs the following major functions: y Controls and interprets all interface signals between the host controller and the drive. y Controls read write accessing of the disk media, including defect management and error recovery.
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4.0 Drive characteristics This section describes the characteristics of the drive. 4.1 Default logical drive parameters The default of the logical drive parameters in Identify Device data is as shown below.
4.
4.3 Drive organization 4.3.1 Drive format Upon shipment from Hitachi Globals Storage Technologies manufacturing the drive satisfies the sector continuity in the physical format by means of the defect flagging strategy described in Section 5.0 on page 19 in order to provide the maximum performance to users. 4.3.
4.4 Performance characteristics Drive performance is characterized by the following parameters: y Command overhead y Mechanical positioning - Seek time - Latency y Data transfer speed y Buffering operation (Look ahead/Write cache) All the above parameters contribute to drive performance. There are other parameters that contribute to the performance of the actual system.
The terms “Typical” and “Max” are used throughout this specification with the following meanings: Typical. The average of the drive population tested at nominal environmental and voltage conditions. Max. The maximum value measured on any one drive over the full range of the environmental and voltage conditions. (See Section 6.4, “Environment” on page 45 and Section 6.5, “DC Power Requirements” on page 47.
4.4.2.4 Cylinder switch time (Cylinder skew) Cylinder switch time - typical (ms) 1.6 72 kTPI Figure 8. Cylinder switch time Cylinder switch time is defined as the amount of time required by the fixed disk to access the next sequential block after reading the last sector in the current cylinder. The measuring method is given in Section 4.4.5, “Throughput” on page 16. 4.4.2.
4.4.4 Data transfer speed Data transfer speed 180 GB model (Mbyte/s) Disk-Buffer transfer (Zone 0) Instantaneous - typical Sustained - read typical 66 56.3 Disk-Buffer transfer (Zone 26) Instantaneous - typical Sustained - read typical Buffer-Host (max) 34.5 29.4 100 Figure 12.
4.4.5 Throughput 4.4.5.1 Simple sequential access The following figure illustrates the case of the three-disk enclosure. Operation Sequential Read (Zone 0) Sequential Read (Zone 26) Typical (sec) 0.32 0.61 Max (sec) 0.34 0.64 Figure 13. Simple Sequential Access performance The above table gives the time required to read a total of 8000h consecutive blocks (16,777,216 bytes) accessed by 128 read commands.
Operating mode Description Start up time period from spindle stop or power down Seek operation mode Write operation mode Read operation mode Spindle rotation at 7200 RPM with heads unloaded Spin-up Seek Write Read Unload Idle Idle Spindle motor and servo system are working normally. Commands can be received and processed immediately Actuator is unloaded and spindle motor is stopped. Commands can be received immediately Actuator is unloaded and spindle motor is stopped.
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5.0 Defect flagging strategy Media defects are remapped to the next available sector during the Format Process in manufacturing. The mapping from LBA to the physical locations is calculated by an internally maintained table. Shipped format y Data areas are optimally used. y No extra sector is wasted as a spare throughout user data areas. y All pushes generated by defects are absorbed by the spare tracks of the inner zone. N N +1 d e fe c t s k ip N +2 d e fe c t N +3 s k ip Figure 16.
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6.0 Specification 6.1 Electrical interface 6.1.1 Connector location Refer to the following illustration to see the location of the connectors. Figure 17. Connector location (2- and 3-disk model shown) 6.1.1.1 DC power connector The DC power connector is designed to mate with AMP part number 1-480424-0 using AMP pins part number 350078-4 (strip), part number 61173-4 (loose piece), or their equivalents. Pin assignments are shown in the figure below.
6.1.
DA0-DA2 Address used to select the individual register in the drive. CS0- Chip select signal generated from the Host address bus. When active, one of the Command Block Registers (Data, Error {Features when written}, Sector Count, Sector Number, Cylinder Low, Cylinder High, Drive/Head and Status {Command when written} register) can be selected. (See Figure 43 on page 38.) CS1- Chip select signal generated from the Host address bus.
The drive is configured as either Device 0 or 1 depending upon the value of CSEL. y If CSEL is grounded, the device address is 0 y If CSEL is open, the device address is 1 KEY Pin position 20 has no connection pin. It is recommended to close the respective position of the cable connector in order to avoid incorrect insertion by mistake.
The termination resistors on the device side are implemented on the drive side as follows: y33 Ω for DD0 thru DD15, DMARQ, INTRQ y82 Ω for CS0-, CS1-, DA0, DA1, DA2, DIOR-, DIOW-, DMACKy22 Ω for IORDY 6.1.3 Interface logic signal levels The interface logic signal has the following electrical specifications: Inputs Outputs Input High Voltage Input Low Voltage 2.0 V min. 0.8 V max. Output High Voltage Output Low Voltage 2.4 V min. 0.5 V max.
6.2 Signal timings 6.2.1 Reset timings Drive reset timing. RESETt10 BUSY t14 Figure 21. System reset timing chart PARAMETER DESCRIPTION t10 t14 RESET low width RESET high to not BUSY Min (usec) Max (sec) 25 – 31 Figure 22.
6.2.2 PIO timings The PIO cycle timings meet Mode 4 of the ATA/ATAPI-6 description. CS(1:0) DA(2:0) t9 t1 t0 DIOR-, DIOWt2 t2i Write data DD(15:0) t3 t4 Read data DD(15:0) t5 tA t6 tB IORDY (*) Up to ATA-2 (mode-0,1,2) Figure 23.
6.2.2.2 Read DRQ interval time For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows: y In the event that a host reads the status register only before the sector or block transfer DRQ interval, the DRQ interval 4.2 µs y In the event that a host reads the status register after or both before and after the sector or block transfer, the DRQ interval is 11.
6.2.3 Multiword DMA timings The Multiword DMA timing meets Mode 2 of the ATA/ATAPI-6 description. CS0-/CS1- tM tN tLR/tLW DMARQ tJ t0 DMACKtI tD tKR/tKW DIOR-/DIOWtE tG tZ tF READ DATA tG tH WRITE DATA Figure 25.
6.2.4 Ultra DMA timings The Ultra DMA timing meets Mode 0,1,2,3 4, and 5 of the Ultra DMA Protocol. 6.2.4.1 Initiating Read DMA DMARQ tUI DMACKtACK tENV tACK tENV STOP t2CYC HDMARDY- tCYC tDZFS DSTROBE xxxxxxxxxxxxxxxxxxxxxxxxx tDH tDS tZAD tAZ DD(15:00) tCYC tFS tZIORDY tDH tDS xxx RD Data xxx RD Data xxx RD Data Device drives DD Host drives DD Figure 27.
6.2.4.2 Host Pausing Read DMA DMARQ DMACKSTOP tSR HDMARDYtRFS DSTROBE Figure 29. Ultra DMA cycle timing chart (Host pausing Read) PARAMETER DESCRIPTION (all values in ns) tSR tRFS DSTROBE to HDMARDY– time HDMARDY– to final DSTROBE time MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX – 50 – 30 – 20 – – – – – – – 75 – 70 – 60 – 60 – 60 – 50 Note: When a host does not satisfy tSR timing, it should be ready to receive two more data words after HDMARDY– is negated.
6.2.4.3 Host Terminating Read DMA DMARQ tLI tMLI DMACKtACK tRP STOP tACK HDMARDYtLI tRFS tIORDYZ DSTROBE DD(15:00) tCS tAZ xxx RD Data xxxxxxxxxxxxxxxxxx xxx tCH CRC xxxxxxxxxx tZAH Device drives DD Host drives DD Figure 31.
6.2.4.4 Device Terminating Read DMA DMARQ tSS tMLI DMACKtLI tACK tLI tACK STOP HDMARDYtLI tIORDYZ DSTROBE DD(15:00) tCS tAZ xxxxx xxxxxxxxxxxxxxxxxx tCH xxxxxxxxxx CRC tZAH Host drives DD Device drives DD Figure 33.
6.2.4.5 Initiating Write DMA DMARQ tUI DMACKtACK tENV STOP tZIORDY tLI t2CYC DDMARDYtACK tCYC tUI HSTROBE tDH tDS DD(15:0) tCYC tDS tDH xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data xxx WT Data xxx WT Data Host drives DD Figure 35.
6.2.4.6 Device Pausing Write DMA DMARQ DMACKSTOP tSR DDMARDYtRFS HSTROBE Figure 37.
6.2.4.7 Device Terminating Write DMA DMARQ tLI tRP tMLI DMACKtACK STOP tIORDYZ DDMARDYtACK tLI tRFS HSTROBE tCS DD(15:00) xxx WT Data xxxxxxxxxxxxxxxxxxxxxxxxxx tCH xxxxxxxxxx CRC Host drives DD Figure 39.
6.2.4.8 Host Terminating Write DMA DMARQ tLI tMLI DMACKtACK tSS STOP tLI tIORDYZ DDMARDYtLI tACK HSTROBE tCS DD(15:00) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx tCH CRC xxxxxxxxxx Host drives DD Figure 41.
6.2.5 Addressing of registers The host addresses the drive through a set of registers called the Task File. These registers are mapped into the I/ O space of the host. Two chip select lines (CS0– and CS1–) and three address lines (DA0-02) are used to select one of these registers, while a DIOR– or DIOW– is provided at the specified time. The CS0– is used to address Command Block registers. while the CS1– is used to address Control Block registers. The following table shows the I/ O address map.
6.3 Jumper settings 6.3.1 Jumper pin location Jumper pins Figure 44. Jumper pin location (2- and 3-disk model shown) 6.3.2 Jumper pin identification Pin I Pin A DERA001.prz Pin B Figure 45.
6.3.3 Jumper pin assignment There are four jumper settings as shown in the following sections: y y y y 16 logical head default (normal use) 15 logical head default 2 GB/32 GB clip Power up in standby Within each of these four jumper settings the pin assignment selects Device 0, Device 1, Cable Selection, or Device 1 Slave Present as shown in the following figures. The Device 0 setting automatically recognizes device 1 if it is present.
6.3.4 Jumper positions 6.3.4.1 16 logical head default (normal use) The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 1 (Slave) Present. I G H E F C D A B DEVICE 0 (Master) I G H E F C D A B DEVICE 1 (Slave) I G H E F C D A B CABLE SEL I G H E F C D A B DEVICE 1 I G H E F C D A B Shipping Default Condition (DEVICE 0) (Slave) Present Figure 47. Jumper positions for normal use Notes: 1.
6.3.4.2 15 logical head default The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 1 (Slave) Present setting 15 logical heads instead of default 16 logical head models. I G H E F C D A B DEVICE 0 (Master) I G H E F C D A B DEVICE 1 (Slave) I G H E F C D A B CABLE SEL I G H E F C D A B DEVICE 1 (Slave) Present Figure 48. Jumper positions for 15 logical head default Notes: 1.
6.3.4.3 Capacity clip to 2GB/32GB The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 1 (Slave) Present while setting the drive capacity down either to 2 GB or 32 GB for the purpose of compatibility. I G H E F C D A B DEVICE 0 (Master) I G H E F C D A B DEVICE 1 (Slave) I G H E F C D A B CABLE SEL I G H E F C D A B DEVICE 1 (Slave) Present Figure 49.
6.3.4.4 Power Up In Standby The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 1 (Slave) Present to enable Power Up In Standby. I G H E F C D A B DEVICE 0 (Master) I G H E F C D A B DEVICE 1 (Slave) I G H E F C D A B CABLE SEL I G H E F C D A B DEVICE 1 (Slave) Present Figure 50. Jumper settings for Disabling Auto Spin Notes: 1. These jumper settings are used for limiting power supply current when multiple drives are used. 2.
6.4 Environment 6.4.1 Temperature and humidity Operating conditions Temperature Relative humidity Maximum wet bulb temperature Maximum temperature gradient Altitude Non-Op conditions Temperature Relative humidity Maximum wet bulb temperature Altitude 5 to 55°C 8 to 90% non-condensing 29.4°C non-condensing 15°C/Hour –300 to 3,048 m -40 to 65°C 5 to 95% non-condensing 35°C non-condensing –300 to 12,000 m Figure 51. Temperature and humidity Notes: 1.
Environment Specification 100 36C/95% 90 31C/90% Wet Bulb 35C Relative Humidity (%) 80 Wet Bulb 29.4C 70 60 Nonoperating 50 Operating 40 30 65C/14% 20 55C/15% 10 0 -40 -20 0 20 40 60 Temperature (C) Figure 52. Limits of temperature and humidity Note: Storage temperature range is 0° to 65°. 6.4.2 Corrosion test The drive shows no sign of corrosion inside and outside of the hard disk assembly and is functional after being subjected to seven days at 50°C with 90% relative humidity.
6.5 DC power requirements The following voltage specifications apply at the power connector of the drive. Damage to the drive electronics may result if the power supply cable is connected or disconnected while power is being applied to the drive (no hot plug/unplug is allowed). Connections to the drive should be made in a low voltage, isolated secondary circuit (SELV). There is no special power on/off sequencing required. 6.5.
Power supply current of 120-GB and 80-GB models (values in milliamps.
6.5.3 Power supply generated ripple at drive power connector +5V DC +12V DC Maximum (mV pp) 100 150 MHz 0-10 0-10 Figure 57. Power supply generated ripple at drive power connector During drive start up and seeking 12-volt ripple is generated by the drive (referred to as dynamic loading). If the power of several drives is daisy chained together, the power supply ripple plus the dynamic loading of the other drives must remain within the above regulation tolerance.
6.6 Reliability 6.6.1 Data integrity No more than one sector is lost at Power loss condition during the write operation when the write cache option is disabled. If the write cache option is active, the data in write cache will be lost. To prevent the loss of customer data, it is recommended that the last write access before power off be issued after setting the write cache off. 6.6.
6.7 Mechanical specifications 6.7.1 Physical dimensions 25.4 }0.4 101.6 }0.4 146 BREATHER HOLE (*) Dia. 2.0 38.9 }0.4 19.7 0.4 LEFT }0.1 } FRONT * DO NOT BLOCK THE BREATHER HOLE. Figure 58. Top and side views of 80 GB - 180 GB models with mechanical dimensions All dimensions are in millimeters. Deskstar 180GXP hard disk drive specifications 51 }0.
BREATHER HOLE Figure 59. Bottom and side views of 30GB - 60GB models with breather hole and mounting hole locations All dimensions in the above figure are in millimeters. The breather hole must be kept uncovered in order to keep the air pressure inside of the disk enclosure equal to external air pressure. The following table shows the physical dimensions of the drive. Height (mm) 25.4 ± 0.4 Width (mm) 101.6 ± 0.4 Length (mm) 146.0 ± 0.6 Weight (grams) 640 Figure 60.
6.7.2 Hole locations The mounting hole location and size of the drive are shown below. (4) (6X) Max. penetration 4.5 mm Side View (6) (7) (5) I/F Connector (3) Bottom View (2) (4X) Max. penetration 4.0 mm (1) Thread (1) (2) (3) (4) (5) (6) (7) 6-32 UNC 41.28±0.5 44.45±0.2 95.25±0.2 6.35±0.2 28.5±0.5 60.0±0.2 41.6±0.2 Figure 61. Mounting hole locations All dimensions are in mm.
6.7.3Connector locations Figure 62. Connector locations 6.7.4 Drive mounting The drive will operate in all axes (6 directions). Performance and error rate will stay within specification limits if the drive is operated in the other orientations from which it was formatted. For reliable operation, the drive must be mounted in the system securely enough to prevent excessive motion or vibration of the drive during seek operation or spindle rotation, using appropriate screws or equivalent mounting hardware.
6.8 Vibration and shock All vibration and shock measurements recorded in this section are made with a drive that has no mounting attachments for the systems. The input power for the measurements is applied to the normal drive mounting points. 6.8.1 Operating vibration 6.8.1.1 Random vibration The hard disk drive meets IBM Standard C-S 1-9711-002 (1990-03) for the V5L applied to horizontal direction and V4 applied to vertical direction.
6.8.2.2 Swept sine vibration y 2 G (Zero to peak), 5 to 500 to 5 Hz sine wave y 0.5 oct/min sweep rate y 3 minutes dwell at two major resonances 6.8.3 Operating shock The drive meets IBM Standard C-S 1-9711-007 for the S5 product classification. The drive meets the following criteria while operating in the conditions described below. The shock test consists of 10 shock inputs in each axis and direction for total of 60.
6.9 Acoustics The upper limit criteria of the octave sound power levels are given in Bels relative to one picowatt and are shown in the following table. The sound power emission levels are measured in accordance with ISO 7779. Typical / Max Mode Idle Performance seek mode Operating Quiet seek mode 60-GB, 40GB, & 30-GB models 2.6 / 3.0 3.4 / 3.7 2.8 / 3.2 120-GB and 80-GB models 180-GB model 2.8 / 3.2 3.4 / 3.7 2.9 / 3.3 3.0 / 3.4 3.4 / 3.7 3.1 / 3.5 Figure 67.
6.10 Identification labels The following labels are affixed to every drive shipped from the drive manufacturing location in accordance with the appropriate hard disk drive assembly drawing: A label containing the IBM logo, the IBM part number, and the statement “Made by IBM Japan Ltd.
6.11 Safety 6.11.1 UL and CSA standard conformity The product is qualified per UL 1950 Third Edition and CAN/CSA C22.2 No. 950-M95, Third Edition, for use in Information Technology Equipment including Electric Business Equipment. The UL recognition or the CSA certification is maintained for the product life. The UL and C-UL recognition mark or the CSA monogram for CSA certification appear on the drive. 6.11.
6.12 Electromagnetic compatibility When installed in a suitable enclosure and exercised with a random accessing routine at maximum data rate, the drive meets the following worldwide EMC requirements: y United States Federal Communications Commission (FCC) Rules and Regulations (Class B), Part 15. IBM Corporate Standard C-S 2-0001-026 (A 6 dB buffer shall be maintained on the emission requirements).
Part 2.
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7.0 General This specification describes the host interface of the Deskstar 180GXP hard disk drive. The interface conforms to the Working Document of Information Technology - AT Attachment with Packet Interface Extension (ATA/ATAPI-6), Revision 3b, dated 26 February 2002, with deviations as described in Section 7.2, “Deviations from standard” below. 7.1 Terminology Device The Deskstar 180GXP hard disk drive Host The system to which the device is attached 7.
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8.
8.1 Alternate Status Register Alternate Status Register 7 6 5 BSY RDY DF 4 DSC/ SERV 3 2 1 0 DBQ COR IDX ERR Figure 69. Alternate Status Register This register contains the same information as the Status Register. The only difference is that reading this register does not imply interrupt acknowledge or clear a pending interrupt. See 8.13, “Status Register” on page 70 for the definition of the bits in this register. 8.
8.5 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers which are 8 bits wide. Data transfers are PIO only. The register contains valid data only when DRQ=1 in the Status Register. 8.
-H3,-H2,-H1,-H0 -Head Select. These four bits are the 1's complement of the binary coded address of the currently selected head. -H0 is the least significant. -DS1 -Drive Select 1. Drive select bit for device 1, active low. DS1=0 when device 1 (slave) is selected and active. -DS0 -Drive Select 0. Drive select bit for device 0, active low. DS0=0 when device 0 (master) is selected and active. 8.8 Device/Head Register Device/Head Register 7 6 5 4 3 2 1 0 1 L 1 DRV HS3 HS2 HS1 HS0 Figure 72.
Bit Definitions ICRCE (CRC) Interface CRC Error. CRC=1 indicates a CRC error has occurred on the data bus during Ultra-DMA transfer. UNC Uncorrectable Data Error. UNC=1 indicates an uncorrectable data error has been encountered. IDNF (IDN) ID Not Found. IDN=1 indicates the ID field of the requested sector could not be found. ABRT (ABT) Aborted Command. ABT=1 indicates the requested command has been aborted due to a device status error or an invalid parameter in an output register.
8.13 Status Register Status Register 7 6 5 BSY DRDY DF 4 DSC/ SERV 3 2 1 0 DRQ CORR IDX ERR Figure 74. Status Register This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command. If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this register is read. If BSY=1, no other bits in the register are valid.
9.0 General operation 9.1 Reset response There are three types of resets in ATA: Power On Reset (POR). The device executes a series of electrical circuitry diagnostics, spins up the HDA, tests speed and other mechanical parameters, and sets default values. Hard Reset (Hardware Reset). RESET- signal is negated in ATA Bus. The device resets the interface circuitry as well as Soft Reset. Soft Reset (Software Reset). SRST bit in the Device Control Register is set and then is reset.
9.1.1 Register initialization After power on, hard reset, or software reset, the register values are initialized as shown in the figure below. Register Default Value Diagnostic Code Error Sector Count 01h Sector Number 01h Cylinder Low 00h Cylinder High 00h Device/Head A0h Status 50h Alternate Status 50h Figure 76.
9.2 Diagnostic and reset considerations For each Reset and Execute Device Diagnostic the diagnostic is done as follows: Power On Reset. DASP- is read by Device 0 to determine if Device 1 is present. If Device 1 is present, Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error. Otherwise Device 0 clears the BSY bit whenever it is ready to accept commands. Device 0 may assert DASP- to indicate device activity.
9.3 Sector Addressing Mode All addressing of data sectors recorded on the drive media is by a logical sector address. The logical CHS address for the drive is different from the actual physical CHS location of the data sector on the disk media. The drive supports both Logical CHS Addressing Mode and LBA Addressing Mode as the sector addressing mode.
9.4 Overlapped and queued feature Overlap allows devices to perform a bus release so that the other device on the bus may be used. To perform a bus release the device clears both DRQ and BSY to zero. When selecting the other device during overlapped operations, the host shall disable interrupts via the nIEN bit on the currently selected device before writing the Device/Head register to select the other device.
9.5 Power management feature The power management feature set permits a host to reduce the power required to operate the drive. It provides a set of commands and a timer that enable a device to implement low power consumption modes. The drive implements the following set of functions: y Standby timer y Idle command y Idle Immediate command y Sleep command y Standby command y Standby Immediate command 9.5.1 Power modes The lowest power consumption when the device is powered on occurs in Sleep Mode.
9.5.4 Interface capability for power modes Each power mode affects the physical interface as defined in the following table. Mode BSY RDY Active Idle Standby Sleep X O O X X 1 1 X Interface active Yes Yes Yes No Media Active Active Inactive Inactive Figure 79. Power conditions Ready (RDY) is not a power condition. A device may post ready at the interface even though the media may not be accessible.
9.6 S.M.A.R.T. function The intent of Self-Monitoring Analysis and Reporting Technology (S.M.A.R.T) is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition.
disabled. Disabling SMART disables the delivering of error log information via the SMART READ LOG SECTOR command. If a device receives a firmware modification, all error log data is discarded and the device error count for the life of the device is reset to zero. 9.6.8 Self-test The device provides the self-test features which are initiated by SMART Execute Off-line Immediate command.
9.7 Security Mode Feature Set Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent unauthorized access to a hard disk device even if the device is removed from the computer. The following commands are supported for this feature: Security Set Password Security Unlock Security Erase Prepare Security Erase Unit Security Freeze Lock Security Disable Password ('F1'h) ('F2'h) ('F3'h) ('F4'h) ('F5'h) ('F6'h) 9.7.
The system manufacturer or dealer who intends to enable the device lock function for end-users must set the master password even if only single level password protection is required. 9.7.4 Operation example 9.7.4.1 Master Password setting The system manufacturer or dealer can set a new Master Password from default Master Password using the Security Set Password command without enabling the Device Lock Function. The Master Password Revision Code is set to FFFEh as shipping default by the drive manufacturer.
9.7.4.3 Operation from POR after User Password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed.
9.7.4.4 User Password Lost If the User Password is forgotten and High level security is set, the system user cannot access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.
9.7.5 Command table This table shows the response of the device to commands when the Security Mode Feature Set (Device lock function) is enabled.
Command Seek Service Set Features Locked Mode Unlocked Mode Frozen Mode Executable Executable Executable Command aborted Executable Executable Executable Executable Executable Set Max Address Command aborted Executable Executable Set Max Address Ext Command aborted Executable Executable Set Multiple Mode Executable Executable Executable Sleep Executable Executable Executable SMART Disable Operations Executable Executable Executable SMART Enable/Disable Attributes Autosave E
9.8 Host Protected Area Function The Host Protected Area Function provides a protected area which cannot be accessed via conventional methods. This protected area is used to contain critical system data such as BIOS or system management information. The contents of the main memory of the entire system may also be dumped into the protected area to resume after system power off.
4. Advanced usage using protected area The data in the protected area is accessed by the following method: i. Issue Read Native Max Address command to get the real device maximum LBA. Returned value shows that native device maximum LBA is 12,692,735 (C1ACFFh) regardless of the current setting. ii. Make the entire device including the protected area accessible by setting device maximum LBA as 12,692,735 (C1ACFFh) via the Set Max Address command with the volatile option.
9.9 Seek Overlap The Deskstar 180GXP provides an accurate method for measuring seek time. The seek command is usually used to measure the device seek time by accumulating the execution time for a number of seek commands. With typical implementation of seek command this measurement must include the device and host command overhead. To eliminate this overhead the drive overlaps the seek command as described below. The first seek command is completed before the actual seek operation is ended.
9.10 Write cache function Write cache is a performance enhancement whereby the device reports the completion of the write command (Write Sectors, Write Multiple, and Write DMA) to the host as soon as the device has received all of the data into its buffer. The device assumes the responsibility for subsequently writing the data onto the disk. y While writing data after completed acknowledgment of a write command, soft reset or hard reset does not affect its operation.
9.12 Power-Up In Standby feature set The Power-Up In Standby feature set allows devices to be powered-up into the Standby power management state to minimize inrush current at power-up and to allow the host to sequence the spin-up of devices. This feature set will be enabled and disabled via the SET FEATURES command or the use of a jumper. When enabled by a jumper, the feature set shall not be disabled via the SET FEATURES command. The enabling of this feature set shall be persistent after power cycle.
9.14 Automatic Acoustic Management feature set (AAM) This feature set allows the host to select an acoustic management level. The acoustic management level may range from the lowest acoustic emanation setting of 01h to the maximum performance level of FEh. Device performance and acoustic emanation may increase with increasing acoustic management levels. The acoustic management levels may contain discrete bands.
Before Enable Address Offset Mode A reserved area has been created using a nonvolatile Set Max command. Accessible (User Area) LBA 0 Non-Accessible (System reserved area) LBA R LBA M After Enable Address Offset Mode Accessible (System reserved area) LBA 0 Non-Accessible (User area) LBA M–R LBA M After Set Max Address Command using the Value Returned by Read Max Address Any commands which access sectors across the LBA M–R are aborted with error.
9.16 48-bit Address Feature Set The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred by a single command are increased by increasing the allowable sector count to 16 bits.
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10.0 Command Protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check if BSY=1, and should proceed no further unless and until BSY=0. For all commands, the host must also wait for RDY=1 before proceeding. A device must maintain either BSY=1 or DRQ=1 at all times until the command is completed.
10.1 PIO Data In commands These commands are y Device Configuration Identify y Identify Device y Read Buffer y Read Log Ext y Read Long y Read Multiple y Read Multiple Ext y Read Sector(s) y Read Sector(s) Ext y S.M.A.R.T. Read Attribute Values y S.M.A.R.T. Read Attribute Thresholds y S.M.A.R.T. Read Log Sector Execution includes the transfer of one or more 512 byte (>512 bytes on Read Long) sectors of data from the device to the host. 1.
Note that the status data for a sector of data is available in the Status Register before the sector is transferred to the host. If the device detects an invalid parameter, it will abort the command by setting BSY=0, ERR=1, ABT=1, and interrupting the host. If an error occurs, the device will set BSY=0, ERR=1, and DRQ=1. The device will then store the error status in the Error Register and interrupt the host. The registers will contain the location of the sector in error.
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f. The device clears the interrupt in response to the Status Register being read. The Write Multiple command transfers one block of data for each interrupt. The other commands transfer one sector of data for each interrupt. If the device detects an invalid parameter, it will abort the command by setting BSY=0, ERR=1, ABT=1, and interrupting the host. If an uncorrectable error occurs, the device will set BSY=0 and ERR=1, store the error status in the Error Register, and interrupt the host.
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4. When the device has finished processing the command, it sets BSY=0 and interrupts the host. 5. In response to the interrupt, the host reads the Status Register. 6. The device clears the interrupt in response to the Status Register being read.
10.4 DMA commands DMA commands are y Read DMA y Read DMA Ext y Write DMA y Write DMA Ext Data transfers using DMA commands differ in two ways from PIO transfers: y data transfers are performed using the slave DMA channel y no intermediate sector interrupts are issued on multisector commands Initiation of the DMA transfer commands is identical to the Read Sector(s) or Write Sector(s) commands except that the host initializes the slave-DMA channel prior to issuing the command.
10.5 DMA queued commands DMA queued commands are y y y y y Read DMA Queued Read DMA Queued Ext Service Write DMA Queued Write DMA Queued Ext 1. Command Issue a. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers. b. The host writes command code to the Command Register. c. The device sets BSY. d. The device clears or sets REL. e. The device clears BSY. 2. Data Transfer and Command Completion.
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11.0 Command descriptions Commands marked * are alternate command codes for the previously defined command. See the next page for list of Protocol definitions.
Protocol 2 2 3 5 3 3 3 3 3 3 3 3 3 3 1 1 3 3 2 3 3 3 3 3 2 4 4 4 5 5 2 2 2 2 2 2 2 2 Command Security Set Password Security Unlock Seek Service Set Features Set Max Address Set Max Address Ext Set Multiple Mode Sleep Sleep* SMART Disable Operations SMART Enable/Disable Attribute Auto save SMART Enable Operations SMART Execute Off-line Data Collection SMART Read Attribute Values SMART Read Attribute Thresholds SMART Return Status SMART Save Attribute Values SMART Write Log Sector SMART Enable/Disable Automa
Command (Subcommand) Command code (Hex) Feature Register (Hex) B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 D0 D1 D2 D3 D4 D5 D6 D8 D9 DA DB EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF 02 03 05 06 07 09 42 44 55 5D 66 82 85 86 89 AA BB C2 CC DD (S.M.A.R.
R Retry. Original meaning is obsoleted, there is no difference between 0 and 1. (Use of 0 is recommended for future compatibility.). B Option Bit. Indicates that the Option Bit of the Sector Count Register should be specified. (This bit is used by Set Max Address command) V Valid. Indicates that the bit is part of an output parameter and should be specified. x Indicates that the hex character is not used. - Indicates that the bit is not used.
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11.2.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h) The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings. After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION RESTORE commands are aborted by the device. The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power-down.
1 Multiword DMA modes supported 15-3 Reserved 2 1 = Multiword DMA mode 2 and below are supported 1 1 = Multiword DMA mode 1 and below are supported 0 1 = Multiword DMA mode 0 is supported 2 Ultra DMA modes supported 15-6 Reserved 5 1 = Ultra DMA mode 5 and below are supported 4 1 = Ultra DMA mode 4 and below are supported 3 1 = Ultra DMA mode 3 and below are supported 2 1 = Ultra DMA mode 2 and below are supported 1 1 = Ultra DMA mode 1 and below are supported 0 1 = Ultra DMA mode 0 is supported 3-6 Maximu
Cylinder high Cylinder low Sector Number Sector count Invalid word location Invalid bit location (bits (7:0)) Invalid bit location (bits 15:8)) Error reason code & description 01h DCO feature is frozen 02h Device is now Security Locked mode 03h Device feature is already modified with DCO 04h User attempt to disable any feature enabled 05h Device is now SET MAX Locked or Frozen mode 06h Protected area is now established 07h DCO is not supported 08h Subcommand code is invalid FFh other reason Figure 94.
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11.5 Flush Cache Ext (EAh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High - - - - - - - - Data High - - - - - - - - - - - - - - - - Error Current Feature ...See Below...
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Input parameters from the device Sector Number In LBA mode this register specifies current LBA address bits 0-7. (L=1) Cylinder High/Low In LBA mode this register specifies current LBA address bits 8-15 (Low), 16-23 (High). H In LBA mode this register specifies current LBA address bits 24-27. (L=1) Error The Error Register. An Abort error (ABT=1) will be returned when LBA is out of range. In LBA mode this command formats a single logical track including the specified LBA.
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The Identify Device command requests the device to transfer configuration information to the host. The device will transfer a sector to the host containing the information described in the figure below. Note: * in the Content field indicates vendor specific use of those parameters.
Word 50 Content 4000H 51 52 0200H 0200H 53 0007H 54 55 56 57-58 XXXXH XXXXH XXXXH XXXXH 59 0XXXH 60-61 XXXXH 62 63 0000H XX07H 64 0003H 65 0078H 66 0078H 67 00F0H 68 0078H Description Capabilities, bit assignments: 15-14(=01) Word 50 is valid 13– 1(=0) Reserved 0 Minimum value of Standby timer (=0) less than 5 minutes (=1) equal to or greater than 5 minutes PIO data transfer cycle timing mode y DMA data transfer cycle timing mode.
Word 69-74 75 Content 0000H 00XXH 76-79 80 0000H 007CH 81 0019H 82 74EBH 83 7FEAH Description Reserved Queue depth 15- 5 Reserved 4- 0 Maximum queue depth Reserved Major version number 15- 0 (=7C)ATA-2, ATA-3, ATA/ATAPI-4, ATA/ATAPI-5, and ATA/ATAPI-6 Minor version number 15- 0 (=19)ATA/ATAPI-6 T13 1410D revision 3a Command set supported 15(=0) Reserved 14(=1) NOP command 13(=1) READ BUFFER command 12(=1) WRITE BUFFER command 11(=0) Reserved 10(=1) Host Protected Area feature set 9(=0) DEVICE RESE
Word 84 Content 4023H 85 XXXXH 86 XXXXH 87 4023H Description Command set/feature supported extension 15-14 Word 84 is valid 13- 6 Reserved 5 (=1) General Purpose Logging feature set supported 4- 2 Reserved 1 (=1) SMART self-test supported 0 (=1) SMART error logging supported Command set/feature enabled 15 Reserved 14 NOP command 13 READ BUFFER command 12 WRITE BUFFER command 11 Reserved 10 Host Protected Area feature set 9 DEVICE RESET command 8 SERVICE interrupt 7 RELEASE interrupt 6 LOOK AHEAD 5 W
Word 88 Content 0X3FH 89 XXXXH 90 91 92 93 0000H 0000H FFFEH XXXXH 94 XXXXH Description Ultra DMA transfer modes 15- 8 (=xx) Current active Ultra DMA transfer mode 15-14 Reserved (=0) 13 Mode 5 1= Active 0= Not Active 12 Mode 4 1= Active 0= Not Active 11 Mode 3 1= Active 0= Not Active 10 Mode 2 1= Active 0= Not Active 9 Mode 1 1= Active 0= Not Active 8 Mode 0 1= Active 0= Not Active 7- 0 (=3F) Ultra DMA transfer mode supported 7-6 Reserved (=0) 5 Mode 5 1= Support 4 Mode 4 1= Support 3 Mode 3 1= Sup
Word 95-99 100-103 Content 0000H xxxxH 104-126 127 0000H 0000H 128 XXXXH 129 XXXXH 130-159 XXXXH 160-254 255 0000H XXA5H Description Reserved Minimum user LBA address for 48-bit Address feature set Reserved Removable Media Status Notification feature set 0000H = Not supported Security status.
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R The retry bit. This bit is ignored. Input parameters from the device Sector Count The number of requested sectors not transferred. This will be zero unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High).
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Output Parameters To The Device The number of sectors to be transferred low order, bits (7:0). Sector Count Current The number of sectors to be transferred high order, bits (15:8). If Sector Count Previous 0000h in the Sector Count register is specified, then 65,536 sectors will be transferred.
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Input parameters from the device on bus release Sector Count Bits 7 - 3 (Tag) contain the Tag of the command being bus released. Bit 2 (REL) is set to one. Bit 1 (I/O) is cleared to zero. Bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/low, H n/a. SRV Cleared to zero when the device performs a bus release. This bit is set to one when the device is ready to transfer data.
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Output Parameters To The Device Number of sectors to be transferred low order, bits (7:0). Feature Current Number of sectors to be transferred high order, bits (15:8). 0000h in Feature Previous the Feature register indicates that 65,536 sectors are to be transferred. Bits (7:3) (Tag) contain the Tag for the command being delivered.
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Log address Content Feature set Type 00h Log directory N/A Read Only 03h Extended Comprehensive SMART error log SMART error logging Read Only 06h SMART self-test log SMART self-test See Note 07h Extended SMART self-test log SMART self-test Read Only Host vendor specific SMART Read/Write 80h-9Fh Figure 117. Log Address Definition Note: If log address 06h is accessed using the Read Log Ext or Write Log Ext commands, command abort shall be returned.
11.18.2 Extended Comprehensive SMART Error log The figure below defines the format of each of the sectors that comprise the Extended Comprehensive SMART error log. Error log data structure shall not include errors attributed to the receipt of faulty commands such as command codes not implemented by the device or requests with invalid parameters or in valid addresses.
Data format of each error log structure is shown in the figure below. Description Bytes Offset 1st command data structure 18 00h 2nd command data structure 18 12h 3rd command data structure 18 24h 4th command data structure 18 36h 5th command data structure 18 48h Error data structure 34 5Ah 124 Figure 120. Extended Error log data structure Command data structure: Data format of each command data structure is shown below.
Error data structure: Data format of error data structure is shown below.
11.18.3 Extended Self-test log sector The figure below defines the format of each of the sectors that comprise the Extended SMART self-test log. The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit entries contained in the SMART self-test log, defined in 11.42.6, "Self-test log data structure" on page0 203, shall also be included in the Extended SMART self-test log with all 48-bit entries.
11.18.3.3 Extended Self-test log descriptor entry The content of the self-test descriptor entry is shown below. Description Bytes Offset Self-test number 1 00h Self-test execution status 1 01h Power-on life timestamp in hours 2 02h Self-test failure check point 1 04h Failing LBA (7:0) 1 05h Failing LBA (15:8) 1 06h Failing LBA (23:16) 1 07h Failing LBA (31:24) 1 08h Failing LBA (39:32) 1 09h Failing LBA (47:40) 1 0Ah Vendor specific 15 0Bh 26 Figure 124.
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Input parameters from the device Sector Count The number of requested sectors not transferred. Sector Number The sector number of the transferred sector. (L=0) In LBA mode this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the transferred sector. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the transferred sector. (L=0) In LBA mode this register contains current LBA bits 24-27.
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In LBA mode this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 24 - 27.
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Output Parameters To The Device The number of continuous sectors to be transferred low order, bits Sector Count Current (7:0). The number of continuous sectors to be transferred high order, bits Sector Count Previous (15:8). If 0000h is specified in the Sector Count register, then 65,536 sectors will be transferred. LBA (7:0). Sector Number Current LBA (31:24). Sector Number Previous LBA (15:8). Cylinder Low Current LBA (39:32). Cylinder Low Previous LBA (23:16). Cylinder High Current LBA (47:40).
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Input parameters from the device Sector Count The number of requested sectors not transferred. This will be zero unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the last transferred sector.
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Output Parameters To The Device The number of continuous sectors to be transferred low order, bits (7:0) Sector Count Current The number of continuous sectors to be transferred high order, bits Sector Count Previous (15:8). If zero is specified in the Sector Count register, then 65,536 sectors will be transferred. LBA (7:0). Sector Number Current LBA (31:24). Sector Number Previous LBA (15:8). Cylinder Low Current LBA (39:32). Cylinder Low Previous LBA (23:16). Cylinder High Current LBA (47:40).
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Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 24 - 27.
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Output Parameters To The Device The number of continuous sectors to be verified low order, bits (7:0). Sector Count Current The number of continuous sectors to be verified high order, bits (15:8). Sector Count Previous If zero is specified in the Sector Count register, then 65,536 sectors will be verified. LBA (7:0). Sector Number Current LBA (31:24) Sector Number Previous LBA (15:8). Cylinder Low Current LBA (39:32). Cylinder Low Previous LBA (23:16). Cylinder High Current LBA (47:40).
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Identifier Zero indicates that the device should check the supplied password against the user password stored internally. One indicates that the device should check the given password against the master password stored internally. The Security Erase Unit command erases all user data and disables the security mode feature (device lock function). So after completing this command, all user data will be initialized to zero with write operation.
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Word 00 01-16 17 18-255 Description Control Word bit 0 : bit 1-7 : bit 8 : bit 9-15 : Identifier (1-Master, 0-User) Reserved Security level (1-Maximum, 0-High) Reserved Password (32 bytes) Master Password Revision Code Valid if Word 0 bit 0 = 1 Reserved Figure 142. Security Set Password Information Identifier Zero indicates that device regards Password as User Password. One indicates that device regards Password as Master Password.
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Word Description 01-16 Control Word bit 0 : Identifier (1-Master, 0-User) bit 1-15 : Reserved Password (32 bytes) 17-255 Reserved 00 Figure 144. Security Unlock Information Identifier Zero indicates that device regards Password as User Password. One indicates that device regards Password as Master Password.
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11.36 Service (A2h) Command Block Output Registers Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Feature - - - - - - - - Sector Count - - - - - - - - Sector Number - - - - - - - - Cylinder Low - - - - - - - - Cylinder High - - - - - - - - Device/Head 1 - 1 D - - - - Command 1 1 1 1 0 0 0 0 Figure 146. Service Command (A2h) The Service command is used to provide data transfer or status of a command that was previously bus released or both.
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85H 86H 89H AAH BBH C2H CCH DDH Disable Advanced Power Management Disable Power-up in Standby mode Disable Address Offset mode Enable read look-ahead feature 4 bytes of ECC apply on Read Long/Write Long commands Disable Automatic Acoustic Management Enable reverting to power on defaults Disable release interrupt Note: After a power on reset of hard reset the device is set to the following features as default: Write cache ECC bytes Read look-ahead Reverting to power on defaults Release interrupt : Enable
The idle time to Low power idle mode and Low RPM standby mode vary according to the value in Sector Count register as follows: When Low power idle mode is the deepest Power Saving mode, y 1 = (x − 80h) & 5 + 120 sec (120 [ y 1 [ 435) y 2 =N/A (the device does not go to Low RPM standby mode) When Low RPM standby mode is the deepest Power Saving mode and the value in Sector Count register is between 40h and 7Fh, 120 <= y 1 <= 435 sec (default: 120 sec) y 2 = (x − 40h) & 60 + 600 sec (600 [ y 2 [ 4380) When
The device preserves enabling or disabling of Automatic Acoustic Management and the current Automatic Acoustic Management level setting across all forms of reset, that is, Power on, Hardware, and Software Resets.
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After a successful command completion, Identify Device response words (61:60) shall reflect the maximum address set with this command. If the 48-bit Address feature set is supported, the value placed in Identify Device response words (103:100) shall be the same as the value placed in words (61:60).
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If the device in Address Offset mode receives this command with the nonvolatile option, the device returns aborted error to the host. The device returns the command aborted for a second non-volatile Set Max Address Ext command until next power on or hardware reset. Output Parameters To The Device B Option bit for selection whether nonvolatile or volatile. B=0 is volatile condition. When B=1, MAX Address which is set by Set Max Address Ext command is preserved by POR.
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11.42 S.M.A.R.T.
11.42.1 S.M.A.R.T. Subcommand In order to select a subcommand the host must write the subcommand code to the Features Register of the device before issuing the S.M.A.R.T. Function Set command. The subcommands and their respective codes are listed below.
Upon receipt of the subcommand from the host the device asserts BSY, enables or disables the Autosave feature, clears BSY, and asserts INTRQ. 11.42.1.4 SMART Save Attribute Values (Subcommand D3h) This subcommand causes the device to immediately save any updated Attribute Values to the Attribute Data sector of the device regardless of the state of the Attribute Autosave feature.
11.42.1.6 SMART Read Log Sector (Subcommand D5h) This command returns the specified log sector contents to the host. The 512 bytes data are returned at a command and the Sector Count value shall be set to one. The Sector Number shall be set to specify the log sector address.
Operations command will be preserved in the Attribute Data Sectors of the device. If the device is re-enabled, these Attribute Values will be updated as needed upon receipt of a SMART Read Attribute Values or SMART Save Attribute Values command. 11.42.1.10 SMART Return Status (Subcommand DAh) This command is used to communicate the reliability status of the device upon the request of the host.
11.42.2 Device Attributes Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the SMART Read Attribute Values subcommand. All multibyte fields shown in these data structures are in byte ordering, that is, the least significant byte occupies the lowest numbered byte address location in the field. Description Data Structure Revision Number 1st Device Attribute ... ...
11.42.2.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure. Description Attribute ID Number (01h to FFh) Status flags Attribute Value (valid values from 01h to FDh) Vendor Specific Total Bytes Byte 1 2 1 8 12 Offset 00h 01h 03h 04h Figure 160. Individual Attribute Data Structure Attribute ID Numbers Any nonzero value in the Attribute ID Number indicates an active attribute.
Status Flag definitions Bit 0 1 2-5 Definition Pre-failure/advisory bit 0 An attribute value less than or equal to its corresponding attribute threshold indicates an advisory condition where the usage or age of the device has exceeded its intended design life period. 1 An attribute value less than or equal to its corresponding attribute threshold indicates a pre-Failure condition where imminent loss of data is being predicted.
11.42.2.5 Total time in seconds to complete off-line data collection activity This field tells the host how many seconds the device requires to complete the off-line data collection activity. 11.42.2.
The Data Structure Checksum is the two's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data structure. 11.42.3 Device Attribute Thresholds Data Structure The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by the host in its entirety using the SMART Read Attribute Thresholds.
11.42.3.5 Data Structure Checksum The Data Structure Checksum is the two's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data structure. 11.42.4 SMART Log Directory The figure below defines the 512 bytes that make up the SMART Log Directory. The SMART Log Directory is SMART Log Address zero and is defined as one sector long.
11.42.5 SMART summary error log sector The following figure defines the 512 bytes that make up the SMART summary error log sector. All multibyte fields shown in this data structure follow the ATA/ATAPI-6 specifications for byte ordering.
11.42.5.4 Error log data structure Data format of error data structure is shown below. Description Byte Offset 1st command data structure 12 00h 2nd command data structure 12 0Ch 3rd command data structure 12 18h 4th command data structure 12 24h 5th command data structure 12 30h Error data structure 30 3Ch 90 Figure 165. Error log data structure Command data structure Data format of each command data structure is shown below.
Error data structure: Data format of error data structure is shown below. Description Byte Offset Reserved 1 00h Error register 1 01h Sector count register 1 02h Sector number register 1 03h Cylinder Low register 1 04h Cylinder High register 1 05h Device/Head register 1 06h Status register Extended error data (vendor specific) State 1 07h 19 08h 1 1Bh Life time stamp (hours) 2 1Ch 30 Figure 167.
11.42.6 Self-test log data structure The following figure defines the 512 bytes that make up the Self-test log sector. All multibyte fields shown in these data structures follow the ATA/ATAPI-5 specifications for byte ordering.
11.42.7 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device. Status Register Error Register A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the Cylinder High and Cylinder Low registers. 51h 04h A S.M.A.R.T.
11.
Output Parameters To The Drive Sector Count Time-out Parameter. If it is 0, the time-out interval (Standby Timer) is NOT disabled. If it is nonzero, the automatic power down sequence is enabled.
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Input parameters from the device Sector Count The number of requested sectors not transferred. This will be zero unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the last transferred sector.
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Output Parameters To The Device Sector Count Current The number of continuous sectors to be transferred low order, bits (7:0). Sector Count Previous The number of continuous sectors to be transferred high order bits (15:8). If zero is specified in the Sector Count register, then 65,536 sectors will be transferred. Sector Number Current LBA (7:0). Sector Number Previous LBA (31:24). Cylinder Low Current LBA (15:8). Cylinder Low Previous LBA (39:32). Cylinder High Current LBA (23:16).
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Input parameters from the device on bus release Sector Count Bits 7 - 3 (Tag) contain the Tag of the command being bus released. Bit 2 (REL) is set to one. Bit 1 (I/O) is cleared to zero. Bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/Low, H n/a. SRV Cleared to zero when the device performs a bus release. This bit is set to 1 when the device is ready to transfer data.
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Output Parameters To The Device Sector Count Current number of sectors to be transferred low order, bits (7:0). number of sectors to be transferred high order, bits (15:8). A value of 0000h in the Feature register indicates that 65,536 sectors are to be transferred. bits 7 - 3 (Tag) contain the Tag for the command being delivered. Sector Number Current LBA (7:0). Sector Number Previous LBA (31:24). Cylinder Low Current LBA (15:8). Cylinder Low Previous LBA (39:32).
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Output Parameters To The Device Sector Count Current The number of sectors to be written to the specified log low order, bits (7:0). Sector Count Previous The number of sectors to be written to the specified log high orders, bits (15:8). If the number of sectors is greater than the number indicated in the Log directory, which is available in Log number zero, the device shall return command aborted.
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Input parameters from the device Sector Count The number of requested sectors not transferred. Sector Number The sector number of the sector to be transferred. (L=0) In LBA mode this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the sector to be transferred. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the sector to be transferred.
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Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current 1.5 LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 24 - 27.
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Output Parameters To The Device The number of continuous sectors to be transferred low order, bits (7:0) Sector Count Current The number of continuous sectors to be transferred high order, bits Sector Count Previous (15:8). If zero is specified in the Sector Count register, then 65,536 sectors shall be transferred. LBA (7:0). Sector Number Current LBA (31:24). Sector Number Previous LBA (15:8). Cylinder Low Current LBA (39:32). Cylinder Low Previous LBA (23:16). Cylinder High Current LBA (47:40).
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Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 24 - 27.
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Output Parameters To The Device The number of continuous sectors to be transferred low order, bits Sector Count Current (7:0). The number of continuous sectors to be transferred high order bits Sector Count Previous (15:8). If zero is specified, then 65,536 sectors will be transferred. LBA (7:0). Sector Number Current LBA (31:24). Sector Number Previous LBA (15:8). Cylinder Low Current LBA (39:32). Cylinder Low Previous LBA (23:16). Cylinder High Current LBA (47:40).
12.0 Timings The timing of BSY and DRQ in Status Register is shown in the figure below.
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Index A F Abbreviations used, 1 Acoustics, 57 Actuator, 7 Address Offset, 91 Addressing of registers, 38 Advanced Power Management, 90 AT signal connector, 21 Automatic Acoustic Management, 91 Average latency, 14 Flammability, 59 Formatted Capacity, 9 Full stroke seek, 13 G General features, 3 German Safety Mark, 59 H Head disk assembly, 7 Head switch time, 13 Heads unload and actuator lock, 54 Hole locations, 53 Host Protected Area Function, 86 Humidity, 45 C Cable noise interference, 50 Cabling, 38
P Passwords, 80 Performance characteristics, 12 PIO Data In commands, 96 PIO Data Out commands, 98 PIO timings, 27 PList physical format, 19 Power management, 76 Power modes, 76 Power supply current, 47 Power supply generated ripple, 49 Power-Up In Standby, 90 Preventive maintenance, 50 R Random access, 16 Reassign Function, 89 Registers, 65 Reliability, 50 Reset, 71 Reset timings, 26 S S.M.A.R.T.
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