Datasheet

11.4.7 Device Address Register

–DS0–DS1–H0–H1–H2–H3–WTG–

01234567

Device Address Register

Figure 52. Device Address Register

This register contains the inverted device select and head select addresses of the currently selected

device.

–Drive Select 0. This bit is 0 when device 0 (master) is selected; otherwise it is 1–DS0

–Drive Select 1. This bit is 0 when device 1 (slave) is selected; otherwise it is 1–DS1

–Head Select. These bits are the one's complement of the binary coded address of the

currently selected head. –H0 is the least significant bit

–H3, –H2, –H1, –H0

–Write Gate. This bit is 0 when a write operation is in progress; otherwise it is 1–WTG

DescriptionBit Definitions

Figure 53. Device Address Register bit definitions

11.4.8 Device/Head Register

HS0HS1HS2HS3DRV1L1

01234567

Devic/Head Register

Figure 54. Device/Head Register

This register contains the device and head numbers.

Head Select. These four fits indicate binary encoded address of the head. HS0 is the

least significant bit. At command completion, these bits are updated to reflect the

currently selected head.

The head number may be from zero to the number of heads minus one.

In LBA mode, these bits are updated to reflect the current LBA bits 24–27.

-HS3, -HS2, -HS1, -HS0

Device. When DRV=0, device 0 (master) is selected. When DRV=1, device 1 (slave)

is selected.

DRV

Binary encoded address mode select. When L=0, addressing is by CHS mode. When

L=1, addressing is by LBA mode.

DescriptionBit Definitions

Figure 55. Device/Head Register bit definitions

Hard disk drive specification for DSCM-11000/-10512/-10340