Datasheet

11.4.3 Cylinder High Register

This register contains the high order bits of the starting cylinder address for any disk access. At the end of

the command, this register is updated to reflect the current cylinder number.

In LBA Mode this register contains Bits 16–23. At the end of the command, this register is updated to

reflect the current LBA Bits 16–23.

The cylinder number may be from zero to the number of cylinders minus one.

11.4.4 Cylinder Low Register

This register contains the low order 8 bits of the starting cylinder address for any disk access. At the end

of the command this register is updated to reflect the current cylinder number.

In LBA Mode this register contains Bits 8–15. At the end of the command this register is updated to reflect

the current LBA Bits 8–15.

The cylinder number may be from zero to the number of cylinders minus one.

11.4.5 Data Register

This register is used to transfer data blocks between the device data buffer and the host. It is also the

uration information is transferred on a IDENTIFY DEVICE command.

All data transfers are 16 bits wide except ECC byte transfers, which are 8 bits wide. Data transfers are

PIO only.

The register contains valid data only when DRQ=1 in the Status Register.

11.4.6 Device Control Register

0-IENSRST1––––

01234567

Device Control Register

Figure 50. Device Control Register

This register is used to control the CompactFlash Card interrupt request and to issue an ATA soft reset to

the card. This register can be written even if the device is BUSY.

Interrupt Enable. When –IEN=0, and the device is selected, device interrupts to the host will be

enabled. When –IEN=1, or the device is not selected, device interrupts to the host will be

disabled.

-IEN

Software Reset. The device is held reset when RST=1. Setting RST=0 re-enables the device.SRST (RST)

DescriptionBit Definitions

Figure 51. Device Control Register bit definitions

Hard disk drive specification for DSCM-11000/-10512/-10340