Datasheet

address at offset 8 will provide even data on the low-order byte of the data bus, along with odd data at
offset 9 on the high- order byte of the data bus.
4. The Hitachi Microdrive does not support accessing the Dup. Features and the Dup. Error as word
register at offset 0Ch with CE1 low and CE2 low.
11.3.4 True IDE Mode addressing
ReservedDevice Address11110
Device ControlAlternate Status01110
CommandStatus11101
Device/HeadDevice/Head01101
Cylinder HighCylinder High10101
Cylinder LowCylinder Low00101
Sector NumberSector Number11001
Sector CountSector Count01001
FeaturesError10001
WR DataRD Data00001
-IOWR=0-IORD=0A0A1A2-CE1-CE2
Figure 48. True IDE Mode addressing
The Command Block Registers are used for sending commands to the device or for posting status from
the device.
The Control Block Registers are used for device control and for posting alternate status.
11.4 CF-ATA Registers
11.4.1 Alternate Status Register
ERRIDXCORDRQDSCDFRDYBSY
01234567
Alternate Status Register
Figure 49. Alternate Status Register
This register contains the same information as the Status Register. The only difference is that reading this
register does not imply interrupt acknowledge or clear a pending interrupt. See Section 11.4.13, "Status
Register" on page 62 for the definition of the bits in this register.
11.4.2 Command Register
This register contains the command code being sent to the device. Command execution begins immedi-
ately after this register is written. The command set is shown in Figure 69 on page 86.
All other registers required for the command must be set up before writing the Command Register.
Hard disk drive specification for DSCM-11000/-10512/-10340
58