Datasheet

11.3.3 Memory mapped addressing
3Odd WR DataOdd RD Data91xxxx11
3Even WR DataEven RD Data80xxxx11
Reserved
Device
Address
F1111x01
Device Control
Alternate
Status
E0111x01
2,4Dup. FeaturesDup. ErrorD1011x01
2
Dup. Odd WR
Data
Dup. Odd RD
Data
91001x01
2
Dup. Even WR
Data
Dup. Even RD
Data
80001x01
CommandStatus71110x01
Device/HeadDevice/Head60110x01
Cylinder HighCylinder High51010x01
Cylinder LowCylinder Low40010x01
Sector NumberSector Number31100x01
Sector CountSector Count20100x01
1,2FeaturesError11000x01
1,2Even WR DataEven RD Data00000x01
Notes
-WE=0-OE=0
Offset
A0A1A2A3
A9-
A4
A10-REG
Figure 47. Contiguous I/O mapped addressing
Notes:
1. Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus
and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset
0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address
space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte
register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte
accessed is the odd byte of the equivalent word access. A byte access to address 0 with -CE1 high and
-CE2 low accesses the error (read) or feature (write) register.
2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register
8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte
accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte
accesses to register 8 or 0 will access consecutive (even then odd) bytes from the data buffer. Repeated
word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte
accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8
then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9
access only the odd byte of the data.
3. Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses
between 400h and 7FFh access register 9. This 1 Kbyte memory window to the data register is provided
so that hosts can perform memory to memory block moves to the data register when the register lies in
memory space. Some hosts, such as the X86 processors, must increment both the source and destina-
tion addresses when executing the memory to memory block move instruction. Some PCMCIA socket
adapters also have auto incrementing address logic embedded within them. This address window allows
these hosts and adapters to function efficiently. Note that this entire window accesses the Data Register
FIFO and does not allow random access to the data buffer within the Hitachi Microdrive. A word access to
Hard disk drive specification for DSCM-11000/-10512/-10340
57