Datasheet

11.3 CF-ATA Register Set Definition and Protocol

The drive can be configured as an I/O device through

y Primary I/O mapped address spaces (1F0h–1F7h, 3F6h–3F7h) or secondary I/O mapped

address spaces (170h–177h, 376h–377h)

y Contiguous I/O mapped address spaces; any system decoded 16-byte I/O block

y Memory mapped space

y True IDE mode; only I/O operations to the Task File and Data registers allowed, no PCMCIA

functionality

The communication to or from the card is done using the Task File registers which provide all the neces-

sary registers for control and status information.

11.3.1 Primary or Secondary I/O mapped addressing

ReservedDevice Address11101Fh(17h)0

Device ControlAlternate Status01101Fh(17h)0

CommandStatus11101Fh(17h)0

Device/HeadDevice/Head01101Fh(17h)0

Cylinder HighCylinder High10101Fh(17h)0

Cylinder LowCylinder Low00101Fh(17h)0

Sector NumberSector Number11001Fh(17h)0

Sector CountSector Count01001Fh(17h)0

1,2FeaturesError Register10001Fh(17h)0

1,2Even WR dataEven RD Data00001Fh(17h)0

Notes-IOWR=0-IORD=0A0A1A2A3A9–A4-REG

Figure 45. Primary or Secondary I/O mapped addressing

Notes:

1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = don't care) as a word register on the

combined Odd Data Bus and Even Data Bus (D15–D0). This register may also be accessed by a pair of

byte accesses to the offset 0 with -CE1 low and -CE2 high. The address space of this word register over-

laps the address space of the Error and Feature byte-wide register that lie at offset 1. When accessed

twice as a byte register with -DE1 low, the first byte to be accessed is the even byte of the word and the

second byte accessed is the odd byte of the equivalent word access.

2. A byte access to Register 0 with -CE1 hogh and -CE2 low accesses the error (read) or feature (write)

Hard disk drive specification for DSCM-11000/-10512/-10340