Datasheet

11.2 Card configuration registers
The device has a set of configuration registers in attribute memory space. These registers are used to
control the configurable characteristics of the card. The configurable characteristics include the electrical
interface, I/O address space, interrupt request, and power requirements of the card. These registers also
provide a method for accessing status information about the card. The information can be used to
arbitrate between multiple-interrupt sources on the same interrupt request level. Addresses of the con-
figuration registers are specified by the Configuration registers Base Address in the TPCC_RADR field of
the CISTPL_CONFIG (16-bit PC Card Configuration Tuple) and offset relative to the base address. For
example, the Configuration and Status register can be located at offset 02h from the base address. The
addresses of the card configuration registers should always be read from the CIS since these addresses
may vary in future products.
11.2.1 Configuration Option Register (Offset 00h)
The Configuration Option Register is used to configure the cards interface, address decoding, and inter-
rupt and to issue a soft reset to the device.
Conf0Conf1Conf2Conf3Conf4Conf5LevlREQSRESETR/W
D0D1D2D3D4D5D6D7Operation
Figure 40. Configuration Option Register (Offset 00h)
SRESET: Soft Reset-Setting this bit to one (1), waiting for the minimum reset width time, and returning to
zero (0) places the card in the Reset state. Setting this bit to one (1) is equivalent to the assertion of the
+RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the card in
the same unconfigured Reset state as following power-up and hardware reset. This bit is set to zero (0)
by power-up and hardware reset. Using PCMCIA Soft Reset is considered a hard reset from the ATA
point of view. An ATA soft reset is issued through the Device Control Register.
LevlREQ: This bit is set to one (1) when level mode Interrupt is selected, and zero (0) when pulse mode
is selected. Set to zero (0) by. This bit is set to zero (0) by power-up and hardware reset. When the card
is in Level Mode, the –IREQ pin is pulled up to Vcc on the card and asserted low to signal an interrupt.
The interrupt is kept asserted until the host reads the card status register, thereby resetting the interrupt
indication and causing –IREQ to be deasserted. When the card is in pulse mode, the card signals an
interrupt by the trailing edge of the negative pulse which width is at least 0.5 ms.
Conf5 - Conf0: Configuration Index. This is set to zero (0) by power-up and hardware reset. It is used to
select operation mode of the card as shown below. Conf5 and Conf4 are reserved and must be written as
zero (0).
Secondary I/O mapped, 170h n 177h/376h n 377h110000
Primary I/O mapped, 1F0h n 1F7h/3F6h n 3F7h010000
I/O mapped 16 contiguous registers at any 16-byte
system decoded boundary
100000
Memory mapped000000
Card Configuration ModeConf0Conf1Conf2Conf3Conf4Conf5
Figure 41. Configuration Index
Hard disk drive specification for DSCM-11000/-10512/-10340
52