Datasheet

8.13 True IDE Mode Multiword DMA Data Transfer Timing

The device supports multiword DMA data transfer for Read DMA and Write DMA commands, which are

available in true IDE mode only. In multiword DMA data transfer, INPACK# is used as DMARQ and

REG# is used as DMACK#. Detailed timing specifications are shown in the following two figures. Note

that the fastest transfer timing is equivalent to “DMA Mode 1” as defined in ATA/ATAPI-4 standard.

25DMACK# to tristatetZ

40IOW# to DMARQ delaytLw

40IOR# to DMARQ delaytLr

50IOW# negated pulse widthtKw (*1)

50IOR# negated pulse widthtKr (*1)

5IOR#/DIOW# to DMACK# holdtJ

0DMACK# to IOR#/IOW# setuptI

15IOW# data holdtH

30IOR#/IOW# data setuptG

5IOR# data holdtF

60IOR# data accesstE

IOR#/IOW#tD (*1)

DMACK# to DMARQ delaytC

150

Cycle timet0 (*1)

Maximum

(ns)

Minimum

(ns)

ItemSymbol

Notes:

(*1) t0 is the minimum total cycle time, tD is the minimum command active time, and tK (tKr or tKw, as

appropriate) is the minimum command recovery time or command inactive time. The actual cycle time

equals the sum of the actual command active time and the actual command inactive time. The three tim-

ing requirements of t0, tD, tK shall be met. The minimum tootle cycle time requirement, t0, is greater than

the sum of tD and tK. This means the host can lengthen either tD or tK or both to ensure that t0 is equal

to the value reported in the devices identify drive data.

Figure 35. Multiword DMA data transfer timing data

Hard disk drive specification for DSCM-11000/-10512/-10340