Datasheet

Total Sectors Addressable in LBA Mode
This field contains the number of sectors addressable for the card in LBA mode only.
Multiword DMA Transfer Capability
This field contains the capability of Multiword DMA Transfer. The low order byte identifies by bit all of the
Modes which are supported, e.g., if Mode 0 is supported, bit 0 is set to one. The high order byte contains
a single bit set to indicate which mode is active supported, e.g., if Mode 0 is active, bit 0 is set to one.
Flow Control PIO Transfer modes supported
Bits 7 through 0 of this field is defined as the Advanced PIO Data Transfer Supported Field. This field is
bit significant. Any number of bits may be set in this field by the device to indicate which Advanced PIO
Modes it is capable of supporting.
Of these bits, bits 7 through 2 are Reserved for future Advanced PIO Modes. Bit 0, if set, indicates that
the device supports PIO Mode 3. Bit 1, if set, indicates that the device supports PIO Mode 4.
Note : For backwards compatibility with BIOS written before Word 64 was defined for advanced modes,
a device reports in Word 51 the highest original PIO mode (that is, PIO mode 0, 1, or 2) it can support.
Minimum Multiword DMA Transfer Cycle Time
This field is defined as the Minimum Multiword DMA Transfer Cycle Time Per Word. This field defines, in
nanoseconds, the minimum cycle time that the device can support when performing Multiword DMA
transfers on a per word basis.
Manufacturer's Recommeded Multiword DMA Transfer Cycle Time
This field is defined as the Device Recommended Multiword DMA Transfer Cycle Time. This field defines,
in nanoseconds, the minimum cycle time per word during a single sector host transfer while performing a
multiple sector READ DMA or WRITE DMA command over all locations on the media under nominal
conditions. If a host runs at a faster cycle rate by operating at a cycle time of less than this value, the de-
vice may negate DMARQ for flow control. The rate at which DMARQ is negated could result in reduced
throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control will not be
used, but implies that higher performance may result.
Minimum PIO Transfer Cycle Time with IORDY Flow Control
This field is defined as the Minimum PIO Transfer With IORDY Flow Control Cycle Time. This field
defines, in nanoseconds, the minimum cycle time that the device can support while performing data
transfers while utilizing IORDY flow control.
Command Set Supported
Words 82, 83, and 84 indicate features/command sets supported. Bits 1 through 13 of word 83 and bits 0
through 13 of word 84 are reserved.
Bit 3 of word 82 is set to one, because Hitachi Microdrive supports the Power Management feature
set.
Bit 5 of word 82 is set to one, because Hitachi Microdrive supports write cache.
Bit 6 of word 82 is set to one, because Hitachi Microdrive supports look-ahead.
Bit 12 of word 82 is set to one, because Hitachi Microdrive supports the Write Buffer command.
Bit 13 of word 82 is set to one, because Hitachi Microdrive supports the Read Buffer command.
Bit 14 of word 82 is set to one, because Hitachi Microdrive supports the NOP command.
Bit 2 of word 83 is set to one, because Hitachi Microdrive supports the CFA feature set.
Bit 3 of word 83 is set to one, because Hitachi Microdrive supports the Advanced Power
Management feature set.
Command Set/Feature Enabled
Words 85, 86, and 87 indicate features/command sets enabled. Bits 1 through 15 of word 86 are
reserved. Bits 0-13 of word 87 are reserved.
Bit 3 of word 85 is set to one, if the Power Management feature set has been enabled.
Hard disk drive specification for DSCM-11000/-10512/-10340
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