Hard disk drive specifications Hitachi Microdrive with CF+ Type II interface Models: DSCM-11000 DSCM-10512 DSCM-10340 Revision 4.
Hard disk drive specifications Hitachi Microdrive™ with CF+ Type II interface Models: DSCM-11000 DSCM-10512 DSCM-10340 Revision 4.
1st Revision (Rev 0.1) S07N-6022-01 (Aug. 18, 2000) Preliminary 2nd Revision (Rev 0.2) S07N-6022-02 (Aug. 21, 2000) Preliminary 3rd Revision (Rev 0.3) S07N-6022-03 (Aug. 25, 2000) Preliminary 4th Revision (Rev 1.0) S07N-6022-04 (Aug. 28, 2000) 5th Revision (Rev 2.0) S07N-6022-05 (Octber 26, 2000) 6th Revision (Rev 2.1) S07N-6022-06 (March 12, 2001) 7th Revision (Rev 2.2) S07N-6022-07 (March 29, 2001) 8th Revision (Rev 3.0) S07N-6022-08 (November 13, 2001) 9th Revision (Rev 4.
Table of contents Figures 1.0 1.1 1.2 1.3 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Physical dimensions and weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 Mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.3 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.4 Mounting orientation . . . . . . . . . . . . . . . .
11.2 Card configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 Configuration Option Register (Offset 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Card Configuration Status Register (Offset 02h) . . . . . . . . . . . . . . . . . . . . . . 11.2.3 Pin Replacement Register (Offset 04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.4 Socket and Copy Register (Offset 06h) . . . . . . . . . . . . . . . . . . . . . . .
12.12.1 Metadata Storage Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.0 Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.1 Data In Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.2 Data Out Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.3 Non-Data Commands . . . . . . . . . . . . .
Figures Figure 1. Formatted capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2. Data sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. Performance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Mechanical positioning performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. Full stroke seek time . . . . . .
Figure 50. Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 51. Device Control Register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 52. Device Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 53. Device Address Register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 54. Device/Head Register . . . . . .
Figure 104. Wear Level Command (F5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 105. Write Buffer Command (E8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 106. Write DMA Command (CAh/CBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 107. Write Long Command (32h/33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 108. Write Multiple Command (C5h) . . . . . . . . . . . . . . . . . . . . .
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1.0 General This document describes the characteristics of 1.0-inch 3600-RPM hard disk drive with a CF+ Type II interface and with capacities of 1 GB, 512 MB, and 340 MB. This drive is the Hitachi Microdrive™ and is hereafter referred to as "the drive". This document defines the hardware functional and interface specifications. The drive is available in the following models: • DSCM-11000 • DSCM-10512 • DSCM-10340 The major difference among DSCM-11000, DSCM-10512, and DSCM-10340 is the number of heads.
1.2 Abbreviations Kbpi 1,000 Bits Per Inch Mbps 1,000,000 Bits per second MB 1,048,576 bytes KB 1,000 bytes 32 KB 32 x 1 024 bytes 64 KB 64 x 1 024 bytes Mb/sq.
1.3 Drive handling precautions y The drive can be easily damaged by shocks or Electric Static Discharge (ESD). Any damage incurred by the drive after removal of it from the shipping package and opening of the ESD protective bag is the user’s responsibility. y Do not apply pressing force onto the top or bottom surface of the drive.
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2.0 General features y Compact Flash Type II Card Compliance y 1024 MB, 512 MB and 340 MB formatted capacity y 512 bytes/sector y CF+ Type II Interface y Integrated controller y No-ID recording format y E2PR 32/34 coding y Multizone recording y Enhanced ECC On-The-Fly 40 bytes 3 way Interleaved Reed Solomon Code 5 bytes per interleave On-The-Fly correction y 128 KB (upper 68 KB is used for firmware) Segmented Buffer with write cache y Fast data transfer rate Up to 11.
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Part 1.
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3.0 Fixed disk subsystem description 3.1 Control electronics The control electronics works with the following functions: y Compact Flash Card Interface Protocol y Embedded Sector Servo y No-IDTM format y Multi zone recording y E2PR 32/34 Code y ECC On-The-Fly y Enhanced Adaptive Battery Life Extender 3.
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4.0 Fixed disk characteristics 4.
4.3 Performance characteristics Drive performance is determined by the following parameters: y Command overhead y Mechanical positioning - Seek time - Latency y Data transfer speed y Buffering operation (Look ahead/Write cache) Note: All the above parameters contribute to drive performance. Other parameters also contribute to the performance of the actual system. This specification describes only the characteristics of the drive, not the system throughput which depends on the system and the application.
conditions. (See Section 7.1, “Environment” on page 21. See also Section 7.2, “DC Power Requirements” on page 23.) The seek time is period of time from the start of the motion of the actuator to the start of a reliable read or write operation. A reliable read or write implies that error correction/recovery is not employed to correct arrival problems. The Average Seek Time is a measure of the weighted average of all possible seek combinations.
4.3.2.5 Drive Ready Time/Mode Transition Time Condition Power on to Stand by Stand by to Idle Typical (sec) 0.5 0.5 Maximum (sec) 0.7 0.7 Figure 8. Drive Ready Time 4.3.3 Operating modes Operating mode Description Spin-up Start up time period from spindle stop or power down Seek Seek operation mode Write Write operation mode Read Read operation mode Performance Idle The drive is capable of responding immediately to media access requests.
5.0 Data integrity 5.1 Data loss at power off Power off during any operations except for write operation will not cause any data loss. Power off during a write operation causes the loss of data received by the drive but not yet written onto the disk media. There is a possibility that power off during a write operation might make a maximum of 1 sector of data unreadable. This state can be recovered by a rewrite operation. 5.
5.5 Data buffer test The data buffer is tested at Power-on-reset. The test consists of a write/read "00"x and "ff"x pattern on each buffer position. 5.6 Error recovery Errors occurring on the drive are handled by the error recovery procedure. Errors that are uncorrectable after application of the error recovery procedures are reported to the host system as nonrecoverable errors. 5.7 Automatic reallocation The sectors those show some errors may be reallocated automatically when specific conditions are met.
5.8 ECC A 40-byte three-interleaved ECC processor provides user data verification and correction capability. The first four bytes of ECC are check bytes for user data and the other 36 bytes are Read Solomon ECC bytes. Each interleave has 12 bytes for ECC. Hardware logic corrects up to 15 bytes (5 bytes for each interleave) errors On-the-fly. Following are examples of some error cases. "O" show that this byte contains no error. "X" shows that at least one bit of this byte is bad.
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6.0 File organization The following figure shows the cylinder allocation for the drive. Zone 0 1 2 3 4 5 6 7 8 9 10 11 Cylinder 0–895 896–1791 1792–2431 2432–3327 3328–3839 3840–4223 4224–4607 4608–5375 5376–5759 5760–6399 6400–6911 6912–7167 Sectors per Track 180 180 165 154 150 144 140 135 126 120 112 108 Figure 11.
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7.0 Specification 7.1 Environment 7.1.1 Temperature and humidity Operating conditions Temperature 0–55°C (ambient) (See Note) Relative humidity 8–90%, non condensing Maximum wet bulb temperature 29.
7.1.2 Radiation noise The disk drive must work without degradation of the soft error rate under the following magnetic flux density limit at the enclosure surface. Frequency 0–60 61–100 101–200 201–400 Limits (Gauss RMS) 5 2.5 1 0.5 Figure 13. Radiation noise 7.1.
7.2 DC power requirements Connection to the drive should be made in a safety extra low voltage (SELV) circuit. Power supply Nominal supply Power supply ripple (0-20Mhz) Tolerance Supply current (nominal condition) Performance idle average Low power idle average Read Write Seek average Standby Startup (maximum RMS in 10 ms windows) +3.3V power supply case +3.3 Volts +5V power supply case +5 Volt Notes 70 mV p-p max. 100 mV p-p max.
7.4 Error rates Error rates fall into two categories: y Recoverable errors y Nonrecoverable errors The following error rates assume that no attempts are made to read or write in areas already identified as being defective. The error rates are defined for the drive operating at the full range of environmental conditions and are shown in Section 7.1 “Environment” on page 21. The voltage limits are shown in Section 7.2, “DC Power Requirements” on page 23. 7.4.
7.5 Mechanical specifications 7.5.1 Physical dimensions and weight The following table lists the dimensions and weight of the Hitachi Microdrive. Height (mm) Width (mm) Length (mm) 5.0 + 0.0/–0.1 42.80±0.101 36.40±0.15 Weight (grams) 16 Max. (typical) Figure 15.
7.5.2 Mechanical dimensions Figure 16.
7.5.3 Connector See Section 8.2, “Interface Connector” on page 33. 7.5.4 Mounting orientation The drive will operate in all axes (360°). Performance and error rate will stay within specification limits if the drive is operated in the other permissible orientations from which it was formatted. Thus a drive formatted in a horizontal orientation is able to run vertically and vice versa. Vibration test and shock test are to be conducted by mounting the drive to the test table using a special fixture. 7.5.
7.6.1.2 Operating swept sine vibration y 1 G (Zero-to-peak), 5 to 500 to 5 Hz sine wave y 2.0 oct/min sweep rate 7.6.2 Nonoperating vibration 7.6.2.1 Nonoperating random vibration The test consists of a random vibration applied in each of three mutually perpendicular axes with a 15-minute duration per axis. The Power Spectral Density (PSD) levels for the test simulates the shipping and relocation environment which is shown below. Frequency (Hz) 2.5 5 40 500 Power Spectral Density (g2/Hz) 0.001 0.03 0.
7.7 Acoustics 7.7.1 Sound power level The criteria of A-weighted sound power level is described as follows. Measurements are to be taken in accordance with ISO 7779. The mean of 40 drives is to be less than the typical value. Each drive is to be less than the maximum value. Drives are to meet this requirement in both board down orientations. A-weighted sound power (Bels) Idle Operating Typical Maximum 2.1 2.2 2.4 2.5 Figure 19.
7.8 Identification labels The labels are affixed to every drive. The top side of the label contains y y y y y y y Model name Part number The statement "Made by IBM" Country of origin Notifications to the customer The marks of agencies approval Bar code of the serial numbers The bottom side of the label contains y The IBM logo y The capacity y The product name (Microdrive) Due to space limitations, no additional requirements by customer are allowed. 7.
7.10 Safety 7.10.1 Underwriters Lab (UL) approval All models of the drive comply with UL 1950. 7.10.2 Canadian Standards Authority (CSA) approval All models of the drive comply with CSA C22.2 950-M1995. 7.10.3 IEC compliance All models of the drive comply with IEC 950. 7.10.4 German Safety Mark All models of the drive are approved by TUV on Test Requirement EN 60 950:1988/A1:1990, but the GS mark has not been obtained. 7.10.
y No manufacturing processes for parts or assemblies—including printed circuit boards—use controlled CFC materials. 7.10.8 Secondary circuit protection This product utilizes printed circuit wiring that must be protected against the possibility of sustained combustion due to circuit or component failures as defined in C-B 2-4700-034 (Protection Against Combustion). Adequate secondary over-current protection is the responsibility of the using system.
8.0 Electrical interface specifications The following figure defines all the DC characteristics of the drive. Unless otherwise stated, the following are the electrical interface requirements: y Vcc = 5 ± 5% V y Vcc = 3.3 ± 5% V y Ta = 0–55°C (See Section 7.1, “Environment” on page 21) Symbol Vcc Vi Vo Pd Topr Tstg Item Input power Input Voltage Output Voltage Power consumption Operating Temperature Storage temperature Measurement method with respect to ground Ta = 25°C Conditions –0.3 to 7.0 –0.
8.5 Interface logic signal levels The interface logic signal has the following electrical specifications: Symbol VOH VOL IIH Paramete r "H" Output Voltage "L" Output Voltage "H" Input Current Condition 3.135 V IOH = 2.0 mA (3.135V) 4.0mA (4.75V) IOH = 3.5 mA (3.135 V) 7.0 mA (4.75 V) IOH = –2.5 mA (3.465V) –4.0 mA (5.25 V) IOH = –4.0 mA (3.465 V) –7.0 mA (5.25 V) VIN=VCC VIN = GND PC Card Mode IIL Minimum "L" Input Current VIN = GND IDE Mode READY, INPACK#, BVDI, BVD2 4.
8.6 Attribute Memory Read timing The Attribute Memory access time is defined as 300 ns. Detailed timing specifications are shown in the following two figures.
8.7 Common Memory Read timing Detailed timing specifications are shown in the following figure. Symbol Item tcR taA taCE taOE tdisCE tdisOE tenCE tenOE Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from CE Output Disable time from OE Output Enable Time from CE Output Enable Time from OE Data Valid from Address Change tvA Minimum (ns) 250 Typical (ns) Maximum (ns) 250 250 125 100 100 5 5 0 Figure 24.
8.8 Attribute and Common Memory Write timing The Card Configuration write access time is defined as 250 ns. Detailed timing specifications are shown in the following figure.
8.9 I/O Input (Read) timing Detailed timing specifications are shown in the following two figures.
8.10 I/O Output (Write) timing Detailed timing specifications are shown in the following two figures.
8.11 True IDE Mode I/O Input (Read) Timing Detailed timing specifications are shown in the following two figures.
8.12 True IDE Mode I/O Output (Write) Timing Detailed timing specifications are shown in the following two figures.
8.13 True IDE Mode Multiword DMA Data Transfer Timing The device supports multiword DMA data transfer for Read DMA and Write DMA commands, which are available in true IDE mode only. In multiword DMA data transfer, INPACK# is used as DMARQ and REG# is used as DMACK#. Detailed timing specifications are shown in the following two figures. Note that the fastest transfer timing is equivalent to “DMA Mode 1” as defined in ATA/ATAPI-4 standard.
8.14 Power on/off timing Detailed timing specifications are shown in the following two figures. Symbol Item Condition Vi(CE) Card Enable signal level tsu(VCC) tsu (RESET) trec (Vcc) tpr tpf tw (RESET) th (Hi-zRESET) ts (Hi-zRESET) Card Enable Setup time RESET Setup time Card Enable Recovery time Power rising time Power falling time RESET pulse width 0 V =< VCC < 2 V 2 V =< VCC < VIH Minimum Typ. Max. Units 0 VCC- 0.1 VCC VCC VCC+ 0.1 Volts Volts VCC+ 0.
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Part 2.
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9.0 General 9.1 Introduction This specification describes the host interface of the DSCM-11000, -10512, -10340. The interface conforms to the CF+ and CompactFlash specification with certain limitations described in Section 10.0, “Deviations from Standard.” The drive supports the following new functions included in the CompactFlash specification 1.4 or newer: y Format Unit Function y ENABLE/DISABLE Delayed Write Function y SENSE CONDITION command y Metadata Storage Function 9.
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10.0 Deviations from Standard Standby Timer Standby timer is enabled by STANDBY command or IDLE command. The value in the Sector Count register shall be used to determine the time programmed into the Standby timer. If the Sector Count register is zero, then the Standby timer is set to 109 minutes automatically. Write Verify WRITE VERIFY command does not include read verification after write operation. The function is exactly same as WRITE SECTORS command.
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11.0 System interface 11.1 PCMCIA memory spaces and configuration registers There are two types of memory address space in the drive: common memory and attribute memory. Common memory is the working address space used to map the memory arrays for storing data. It may be accessed by the host for memory read and write operations. The card permits both 8-bit and 16-bit accesses to all of its common memory addresses.
11.2 Card configuration registers The device has a set of configuration registers in attribute memory space. These registers are used to control the configurable characteristics of the card. The configurable characteristics include the electrical interface, I/O address space, interrupt request, and power requirements of the card. These registers also provide a method for accessing status information about the card.
11.2.2 Card Configuration Status Register (Offset 02h) The Card Configuration and Status Register contains information about the card condition. Operation Read Write D7 Changed 0 D6 SigChg SigChg D5 IOis8 IOis8 D4 -XE -XE D3 0 0 D2 PwrDwn PwrDwn D1 Int 0 D0 0 0 Figure 42. Card Configuration Status Register (Offset 02h) Changed: This bit indicates that one or both of the Pin Replacement register CRdy, or CWProt bits are set to one (1).
11.2.3 Pin Replacement Register (Offset 04h) The Pin Replacement Register is used to provide the card status information about READY and WP. Operation Read Write D7 0 0 D6 0 0 D5 CRdy/-Bsy CRdy/-Bsy D4 0 0 D3 1 0 D2 1 0 D1 Rdy/-Bsy MRdy/-Bsy D0 0 0 Figure 43. Pin Replacement Register (Offset 04h) Crdy/-Bsy: This bit is set to one (1) when the bit Rdy/-Bsy changes state. This bit can also be written by the host. Rdy/-Bsy: This bit is used to determine the internal state of the Rdy/-Bsy signal.
11.3 CF-ATA Register Set Definition and Protocol The drive can be configured as an I/O device through y Primary I/O mapped address spaces (1F0h–1F7h, 3F6h–3F7h) or secondary I/O mapped address spaces (170h–177h, 376h–377h) y Contiguous I/O mapped address spaces; any system decoded 16-byte I/O block y Memory mapped space y True IDE mode; only I/O operations to the Task File and Data registers allowed, no PCMCIA functionality.
11.3.2 Contiguous I/O mapped addressing -REG 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 1 0 1 Offset 0 1 2 3 4 5 6 7 8 9 D E F -IORD=0 Even RD Data Error Sector Count Sector Number Cylinder Low Cylinder High Device/Head Status Dup. Even RD Data Dup. Odd RD Date Dup.
11.3.3 Memory mapped addressing -REG A10 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A9A4 x x x x x x x x 1 0 1 A3 A2 A1 A0 Offset -OE=0 -WE=0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 x 1 0 0 0 8 0 x 1 0 0 1 9 1 0 x 1 1 0 1 D Even WR Data Features Sector Count Sector Number Cylinder Low Cylinder High Device/Head Command Dup. Even WR Data Dup. Odd WR Data Dup.
address at offset 8 will provide even data on the low-order byte of the data bus, along with odd data at offset 9 on the high- order byte of the data bus. 4. The Hitachi Microdrive does not support accessing the Dup. Features and the Dup. Error as word register at offset 0Ch with CE1 low and CE2 low. 11.3.
11.4.3 Cylinder High Register This register contains the high order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. In LBA Mode this register contains Bits 16–23. At the end of the command, this register is updated to reflect the current LBA Bits 16–23. The cylinder number may be from zero to the number of cylinders minus one. 11.4.
11.4.7 Device Address Register 7 – 6 –WTG Device Address Register 5 4 3 2 –H3 –H2 –H1 –H0 1 –DS1 0 –DS0 Figure 52. Device Address Register This register contains the inverted device select and head select addresses of the currently selected device. Bit Definitions –WTG Description –Write Gate. This bit is 0 when a write operation is in progress; otherwise it is 1 –Head Select. These bits are the one's complement of the binary coded address of the currently selected head.
11.4.9 Error Register 7 BBK 6 UNC 5 0 Error Register 4 3 IDNF 0 2 ABRT 1 TK0NF 0 AMNF Figure 56. Error Register This register contains status from the last command executed by the device or a diagnostic code. At the completion of any command with the exception of Execute Device Diagnostic, the contents of this register are always valid even if ERR=0 in the Status Register. Bit Definitions BBK UNC IDNF (IDN) ABRT (ABT) TK0NF (T0N) AMNF (AMN) Description Bad Block.
11.4.12 Sector Number Register This register contains the starting sector number for any disk data access for the subsequent command. The sector number is from one to the maximum number of sectors per track. In LBA mode this register contains Bits 0–7. At the end of the command this register is updated to reflect the current LBA Bits 0–7. 11.4.13 Status Register 7 BSY 6 DRDY 5 DF Status Register 4 3 2 DSC DRQ CORR 1 0 0 ERR Figure 58. Status Register This register contains the device status.
12.0 General operational descriptions 12.1 Reset Response There are three types of resets in a CompactFlash device: a power-on reset, a hardware reset, and a software reset. There is also a reset called PCMCIA soft reset, which uses bit 7 of Configuration Option Register. It is treated as a hard reset.
(1) If the device receives a reset during cached writing, the reset completes after cached writing completes (2) Initialized value of task file registers are shown in figure 58 below (3) True IDE mode only (4) If the device has received Set Features with feature code CCh prior to a reset, setting is reverted to the power-on default 12.2 Register Initialization After power on, hard reset, or software reset, the register values are initialized as shown in the following figure.
12.3 Diagnostic and Reset considerations For each Reset and Execute Device Diagnostic, the Diagnostic is done as follows: Power On Reset, Hard Reset DASP- is read by Device 0 to determine if Device 1 is present. If Device 1 is present Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device 0 clears the BSY bit whenever it is ready to accept commands. Device 0 may assert DASP- to indicate device activity.
12.4 Power-off considerations 12.4.1 Load/Unload The product will support a minimum of 300,000 normal load/unloads. The Load/Unload is a functional mechanism of the drive. It is controlled by the drive microcode.
12.4.3 Required power-off sequence Problems can occur on most drives when the power is removed at an arbitrary time. The following are some examples of arbitrary power-off occurrence: y Data loss from the write buffer y If the drive is writing a sector and a partially-written sector with an incorrect ECC block results.
12.6 Power Management Feature The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes. The drive implements the following set of functions: 1. A Standby timer 2. IDLE command 3. IDLE IMMEDIATE command 4. STANDBY command 5. STANDBY IMMEDIATE command 12.6.
12.6.4 Standby timer The standby timer provides a method for the device to automatically enter standby mode from either active or idle mode following a host programmed period of inactivity. If the device is in the active or idle mode the device waits for the specified time period and if no command is received, the device automatically enters the standby mode.
12.7 Advanced Power Management Feature This feature provides power saving without performance degradation. The Adaptive Battery Life Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the device by monitoring access patterns of the host. This technology has three idle modes: Performance Idle mode, Active Idle mode, and Low Power Idle mode. The drive supports Performance Idle mode and Low Power Idle mode.
shorter than the value calculated from the specified level by the SET FEATURE ENABLE ADAPTIVE POWER MANAGEMENT command. The optimal time to enter Performance Idle mode is variable depending on the user's recent behavior. It is not possible to achieve the same level of Power savings with a fixed entry time into Performance Idle because every users data and access pattern is different. The optimum entry time changes over time.
12.8 Seek Overlap The drive provides an accurate seek time measurement method. The SEEK command is usually used to measure the device seek time by accumulating execution time for a number of SEEK commands. With typical implementation of the SEEK command, this measurement must including the device and host command overhead. To eliminate this overhead, the drive overlaps the SEEK command as described below. The first SEEK command completes before the actual seek operation is over.
12.10 Delayed Write Function (Vendor Specific) Delayed Write function is a power saving enhancement whereby the device delays the actual data writing into the media. When the device is in the power saving mode and the write command (WRITE SECTORS, WRITE MULTIPLE, or WRITE DMA) comes from the host, the transferred data is not written into the media immediately. The data is stored in the cache buffer.
12.11 Reassign Function The Reassign Function is used with read and write commands. The sectors of data for reassignment are prepared as the spare data sector. There are 448 spare sectors. One entry can register a maximum of 256 consecutive sectors. This reassignment information is registered internally and the information is available upon completing the reassign function. The information is also used on the next power on reset or hard reset.
12.12 Metadata Storage Function Metadata storage is a small, nonvolatile user area which address space is logically separated from the main storage. The host can use metadata storage to store information on the data contents itself—for example, available free blocks, device properties, or any summary information. The first implementation of metadata storage in the drive provides just 32 bytes, however, the command set design does not preclude any future enhancement.
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13.0 Command Protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined in the following text. For all commands, the host must first check if BSY=1, and should proceed no further unless and until BSY=0. For all commands, the host must also wait for RDY=1 before proceeding. A device must maintain either BSY=1 or DRQ=1 at all times until the command is completed.
13.1 Data In Commands The Data In Commands include the following: y y y y y y y Identify Device Read Buffer Read Long Read Multiple Read Sectors SMART Read Attribute Values SMART Read Attribute Thresholds Execution includes the transfer of one or more 512 byte (>512 bytes on Read Long) sectors of data from the device to the host. The following is a description of the execution process: 1.
error. The errored location will be reported with CHS mode or LBA mode, the mode is decided by mode select bit (bit 6) of Device/Head register on issuing the command. If an Uncorrectable Data Error (UNC=1) occurs, the defective data will be transferred from the media to the sector buffer, and will be available to be transferred to the host, at the host's option.
13.2 Data Out Commands These commands are y y y y y y Format Track Write Buffer Write Long Write Multiple Write Sectors Write Verify Execution includes the transfer of one or more 512 byte (>512 bytes on Write Long) sectors of data from the host to the device. The following is a description of the execution process: 1. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head Registers. 2. The host writes the command code to the Command Register. 3.
All data transfers to the device through the Data Register are 16 bits with the exception of the ECC bytes, which are 8 bits. 13.
13.4 DMA Data Transfer Commands The drive supports DMA Data Transfer Commands ONLY in True IDE mode.
13.5 CF-ATA Command Description This section defines the format of the commands the host sends to the drive. Commands are issued to the card by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command Register. The manner in which a command is accepted varies. There are three classes (see Table below) of command acceptance, all dependent on the host not issuing commands unless the card is not busy (BSY=0).
Class 1 1 1 1 2 2 2 3 3 2 2 3 COMMAND Standby Standby Immediate Translate Sector Wear Level Write Buffer Write DMA Write Long Sector Write Multiple Write Multiple w/o erase Write Sector(s) Write Sector(s) w/o Erase Write Verify Code E2h or 96h E0h or 94h 87h F5h E8h CAh or CBh 32h or 33h C5h FR - SC Y Y Y SN Y Y Y Y CY Y Y Y Y DH D D Y Y D Y Y Y LBA Y Y Y Y CDh - Y Y Y Y Y 30h or 31h - Y Y Y Y Y 38h - Y Y Y Y Y 3Ch - Y Y Y y Y Figure 69.
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Inquiry Metadata Storage (subcommand code - 02h) enables host to read capacity of the Metadata Storage of the device along with information associated with the charasteristics of the Metadata Storage. The data returned from the device is in following format.
The commands that affect media status are y y y y y y y y Write Sectors Write Sectors without Erase Write Long Write Verify Write Multiple Write Multiple without Erase Erase Sectors Format Track Note: the list may grow if new commands are received that change the media contents. word 0 1-32 33-255 data xxxxh xxxxh 0000h description ignored metadata (32 bytes) reserved Figure 74. Data format of Write Metadata Storage Word 0 is a pad and metadata starts with the word 1.
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Output Parameters To The Device Sector Number In LBA mode, this register specifies LBA address bits 0 - 7 to be formatted. (L=1) Cylinder High/Low The cylinder number of the track to be formatted. (L=0) In LBA mode, this register specifies LBA address bits 8 - 15 (Low), 16 - 23 (High) to be formatted. (L=1) H The head number of the track to be formatted. (L=0) In LBA mode, this register specifies LBA address bits 24 - 27 to be formatted.
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Word Address Default Value 0 848Ah Total Bytes Data Field Type Information 2 General configuration - signature for the CompactFlash Storage Card 2 Default number of cylinders 2 2 2 Reserved Default number of heads Default number of sectors per track 4 Number of sectors per card (Word 7 = MSW, Word 8 = LSW) 10-19 22 0828h (0414h) (02B7h) 0000h 0010h 003Fh 1D800020h (0EC00010h) (B090000Ah) aaaa 0004h 23-26 aaaa 8 27-46 aaaa 40 47 8010h 2 49 51 52 53 54 55 56 0F00h 0002h 0001h 0003h X
Default Number of Cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders. Default Number of Heads This field contains the number of translated heads in the default translation mode. Default Number of Sectors per Track This field contains the number of sectors per track in the default translation mode. Number of Sectors per Card This field contains the number of sectors per card.
Total Sectors Addressable in LBA Mode This field contains the number of sectors addressable for the card in LBA mode only. Multiword DMA Transfer Capability This field contains the capability of Multiword DMA Transfer. The low order byte identifies by bit all of the Modes which are supported, e.g., if Mode 0 is supported, bit 0 is set to one. The high order byte contains a single bit set to indicate which mode is active supported, e.g., if Mode 0 is active, bit 0 is set to one.
Bit 6 of word 85 is set to one, if the look-ahead has been enabled. Bit 7 of word 85 is set to one, if the write cache has been enabled. Bit 12 of word 85 is set to one, if the Write Buffer command has been enabled. Bit 13 of word 85 is set to one, if the Read Buffer command has been enabled. Bit 14 of word 85 is set to one, if the NOP command has been enabled. Bit 2 of word 86 is set to one, if the CFA feature set has been enabled.
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Output Parameters To The Device Sector Count The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred. Sector Number The sector number of the first sector to be transferred. (L=0) In LBA mode, this register specifies LBA address bits 0 - 7 to be transferred. (L=1) Cylinder High/Low The cylinder number of the first sector to be transferred. (L=0) In LBA mode, this register specifies LBA address bits 8 - 15 (Low) 16 - 23 (High) to be transferred.
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Output Parameters To The Device Sector Count The number of continuous sectors to be transferred. The Sector Count must be set to one. Sector Number The sector number of the sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the sector to be transferred.
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Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 8-15 (Low), 16-23 (High). (L=1) H The head number of the last transferred sector.
Output Parameters To The Device Sector Count The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred. Sector Number The sector number of the first sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the first sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the first sector to be transferred.
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Input Parameters From The Device Sector Count The number of requested sectors not verified. This will be zero, unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the last transferred sector.
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The following table defines the valid extended error codes for the Hitachi Microdrive. The extended error code is returned to the host in the Error Register.
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The Set Feature command establishes the following parameters which affect the execution of certain features as shown in the table below ABT will be set to 1 in the Error Register if the Feature register contains any undefined values.
Feature 85h is used to disable advanced power management. This results in the same effect as the host uses features 05h with the Sector Count Register FEh. 13.5.
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Address Information 00h-01h Cylinder MSB (00), Cylinder LSB (01) 02h Head 03h Sector 04h-06h LBA MSB (04) - LSB (06) 07h-12h Reserved 13h Erased Flag (FFh) = Erased; 00h = Not Erased 14h-17h Reserved 18h-1Ah Hot Count MSB (18) - LSB (1A) 1Bh-1FFh Reserved Figure 103.
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Output Parameters To The Device Sector Count The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred. Sector Number The sector number of the first sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the first sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High).
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Input Parameters From The Device Sector Count The number of requested sectors not transferred. Sector Number The sector number of the sector to be transferred. (L=0) In LBA mode, this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the sector to be transferred. (L=0) In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the sector to be transferred.
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Sector Count Sector Number Cylinder High/Low H The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs. The sector number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 0 - 7. (L=1) The cylinder number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) The head number of the last transferred sector.
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Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 0 - 7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) H The head number of the last transferred sector.
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13.6 Error Posting The following table summarizes the valid status and error value for all the CF-ATA Command set.
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14.0 Card information structure 00 01 CISTPL_DEVICE (5V Device Information Tuple) 02 03 Tuple length = 4 bytes Device Info fields 04 DB Device ID Device Type (bit4..7) = D (DTYPE_FUNCSPEC) WPS (write protect switch) (bit3) = 1 (non WP) Device Speed (bit0..2) = 3 (DSPEED_150NS) 06 01 08 FF End Mark 0A 1C CISTPL_DEVICE_0C (Additional Device Information Tuple) 0C 04 Tuple length = 4 bytes 0E 03 Other Condition Info Device Size Ext = 1 (2K bytes) (bit7) = 0 Reserved (bit3..
28 00 v 2A 15 CISTPL_VERS_1 (Level1 Version Tuple) 2C 12 Tuple length = 17h bytes 2E 04 Major Version = 4 (JEIDA 4.2/PCMCIA 2.
6E 05 Tuple length = 5 bytes 70 01 TPCC_SZ (Size of Fields Byte) TPCC_RASZ (Size of TPCC_RADR) (bit0,1) = 1 (2bytes) TPCC_RMSZ (Size of TPCC_RMSK) (bit2..
Exponent (bit0..2) = 5 (1V) --> 4.5 V Mantissa (bit3..6) = 9 (4.5) 8A 5D Power Parameter Definition (MaxV) Exponent (bit0..2) = 5 (1V) --> 5.5 V Mantissa (bit3..6) = C (5.5) 8B 4E Power Parameter Definition (PeakI) Exponent (bit0..2) = 6 (100mA) --> 450 mA Mantissa (bit3..6) = 9 (4.5) TPCE_MS (Memory Space Description Structure) 8C 08 Memory Space Descriptor Byte # of Windows (-1) (bit0..2) = 0 (# of window = 1) Length Size (bit3..4) = 1 (length field size = 1 byte) Card Address Size (bit5..
MaxV (bit2) = 0 PeakI (bit5) = 1 9C B5 Power Parameter Definition (NomV) Exponent (bit0..2) = 5 (1V) --+-> 3.3 V Mantissa (bit3..6) = 6 (3.0) + Extension (bit7) = 1 (extension exists) + 9E 1E Extension A0 3E Power Parameter Definition (PeakI) = 1Eh = +0.30 --+ Exponent (bit0..2) = 6 (100mA) --> 350 mA Mantissa (bit3..6) = 7 (3.
Mantissa B0 4D (bit3..6) = A (5.0) Power Parameter Definition (MinV) Mantissa (bit0..2) = 5 (1V) J 4.5 V Exponent (bit3..6) = 9 (4.5) B2 5D Power Parameter Definition (MaxV) Exponent (bit0..2) = 5 (1V) J 5.5 V Mantissa (bit3..6) = C (5.5) B4 4E Power Parameter Definition (PeakI) Exponent (bit0..2) = 6 (100mA) J 450 mA Mantissa (bit3..6) = 9 (4.5) B6 64 TPCE_IO (I/O space address required for this configuration) IO Address Lines (bit0..
Interrupt (bit4) = 0 Memory (bit5,6) = 00 Misc (bit7) = 0 TPCE_PD (Power Description Structure) C8 21 Parameter Selection Byte NomV (bit0) = 1 MinV (bit1) = 0 MaxV (bit2) = 0 PeakI (bit5) = 1 CA B5 Power Parameter Definition (NomV) Exponent (bit0..2) = 5 (1V) --+-> 3.3 V Mantissa (bit3..6) = 6 (3.0) + Extension (bit7) = 1 (extension exists) + CC 1E Extension CE 3E Power Parameter Definition (PeakI) = 1Eh = +0.30 Exponent (bit0..2) = 6 (100mA) --+ --> 350 mA Mantissa (bit3..
DA 27 Parameter Selection Byte NomV (bit0) = 1 MinV (bit1) = 1 MaxV (bit2) = 1 PeakI (bit5) = 1 DC 55 Power Parameter Definition (NomV) Exponent (bit0..2) = 5 (1V) Mantissa DE 4D (bit3..6) = A (5.0) Power Parameter Definition (MinV) Exponent (bit0..2) = 5 (1V) Mantissa E0 5D Power Parameter Definition (MaxV) Mantissa 4E Power Parameter Definition (PeakI) Mantissa EA J 5.5 V (bit3..6) = C (5.5) Exponent (bit0..2) = 6 (100mA) E4 J 4.5 V (bit3..6) = 9 (4.5) Exponent (bit0..
F6 20 TPCE_MI (Miscellaneous Features Field) Max Twin Card (bit0..2) = 0 Audio (bit3) =0 Read Only (bit4) =0 Power Down (bit5) = 1 (support power down mode) F8 1B CISTPL_CFTABLE_ENTRY(16bit PCCard Configuration Table Entry Tuple) FA 06 Tuple length = 06h bytes FC 02 TPCE_INDX (Configuration Table Index Byte) Config Entry Number (bit0..
Interface 110 41 (bit7) = 1 (interface field exist) TPCE_IF (Interface Description Field) Interface Type (bit0..
# of address range -1 (bit0..3) = 1 (# of field = 2) size of address (bit 4,5) = 2 (2byte address) size of length (bit 6,7) = 1 (1byte length) 122 70 I/O address range description field #1 address = 170 124 01 | 126 07 V 228 76 I/O address range description field #2 address = 376 12A 03 | 12C 01 V 12E EE TPCE_IR (Interrupt Request Description structure) 130 20 address block length = 8 address block length = 2 IRQ line 0..15 (bit0..
MaxV (bit2) = 0 PeakI (bit5) = 1 13C B5 Power Parameter Definition (NomV) Exponent (bit0..2) = 5 (1V) Mantissa (bit3..6) = 6 (3.0) Extension (bit7) = 1 (extension exists) + 13E 1E Extension 140 3E Power Parameter Definition (PeakI) = 1Eh = +0.30 Exponent (bit0..2) = 6 (100mA) --+-> 3.3 V + --+ J 350 mA Mantissa (bit3..6) = 7 (3.
Index A Acoustics, 29 Adaptive Battery Life Extender 3, 70 Adaptive Power Save Control, 14 Addressing Mode, LBA, 67 Addressing Mode, Logical CHS, 67 Advanced Power Management, 70 Altitude, 21 Auto Reassign, 74 Automatic reallocation, 16 Electromagnetic compatibility, 30 ENABLE/DISABLE DELAYED WRITE, 73 Environment, 21 Equipment status, 15 Error Posting, 135 Error rates, 24 Error recovery, 16 Errors, nonrecoverable, 24 Errors, recoverable, 24 F Fixed disk characteristics, 11 Flammability, 31 C Cabling, 33
Mode Transition Time, 14 Mounting orientation, 27 O Seek Time, Single Track, 13 Shock, 27 Signal definition, 33 Signal description, 33 Sound power level, 29 Operating modes, 14 T P Packaging, 32 Performance characteristics, 12 Power Management, 68 Power Management Commands, 68 Power Modes, 68 Power requirements, 23 Power-off, 66 Power-off sequence, 67 Preventive maintenance, 23 Temperature, 21 Timing, Attribute and Common Memory Read, 37, 42 Timing, Attribute Memory Read, 35 Timing, Common Memory Read,
© Copyright Hitachi Global Storage Technologies Hitachi Global Storage Technologies 5600 Cottle Road San Jose, CA 95193 Produced in the United States 1/03 All rights reserved DeskstarTM is a trademark of Hitachi Global Storage Technologies. Microsoft, Windows XP, and Windows are trademarks of Microsoft Corporation in the United States, other countries, or both. Other product names are trademarks or registered trademarks of their respective companies.
Hard disk drive specification for DSCM-11000/-10512/-10340 152
