Data Sheet

HEF4013B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 6 of 16
NXP Semiconductors
HEF4013B
Dual D-type flip-flop
11. Dynamic characteristics
Table 7. Dynamic characteristics
T
amb
= 25  C; unless otherwise specified. For test circuit see Figure 6.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ Max Unit
t
PHL
HIGH to LOW
propagation delay
nCP to nQ, nQ;
see Figure 4
5 V
[1]
83 + 0.55  C
L
- 110 220 ns
10 V 34 + 0.23  C
L
- 4590ns
15 V 22 + 0.16  C
L
- 3060ns
nSD to nQ
5 V
[1]
73 + 0.55  C
L
- 100 200 ns
10 V 29 + 0.23  C
L
- 4080ns
15 V 22 + 0.16  C
L
- 3060ns
nCD to nQ 5 V
[1]
73 + 0.55  C
L
- 100 200 ns
10 V 29 + 0.23  C
L
- 4080ns
15 V 22 + 0.16  C
L
- 3060ns
t
PLH
LOW to HIGH
propagation delay
nCP to nQ, nQ;
see Figure 4
5 V
[1]
68 + 0.55  C
L
-95190ns
10 V 29 + 0.23  C
L
- 4080ns
15 V 22 + 0.16  C
L
- 3060ns
nSD to nQ 5 V
[1]
48 + 0.55  C
L
-75150ns
10 V 24 + 0.23  C
L
- 3570ns
15 V 17 + 0.16  C
L
- 2550ns
nCD to nQ
5 V
[1]
33 + 0.55  C
L
-60120ns
10 V 19 + 0.23  C
L
- 3060ns
15 V 12 + 0.16  C
L
- 2040ns
t
t
transition time see Figure 4 5 V
[1]
10 + 1.00  C
L
-60120ns
10 V 9 + 0.42  C
L
- 3060ns
15 V 6 + 0.28  C
L
- 2040ns
t
su
set-up time nD to nCP;
see Figure 4
5 V 40 20 - ns
10 V 25 10 - ns
15 V 15 5 - ns
t
h
hold time nD to nCP;
see Figure 4
5 V 20 0 - ns
10 V 20 0 - ns
15 V 15 0 - ns
t
W
pulse width nCP input LOW;
see Figure 4
5 V 60 30 - ns
10 V 30 15 - ns
15 V 20 10 - ns
nSD input HIGH;
see Figure 5
5 V 50 25 - ns
10 V 24 12 - ns
15 V 20 10 - ns
nCD input HIGH;
see Figure 5
5 V 50 25 - ns
10 V 24 12 - ns
15 V 20 10 - ns