User's Manual

AP6255 Datasheet
AMPAK Technology Inc. www.ampak.com.tw
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19
10.1 SDIO Pin Description
All three package options of the WLAN section provide support for SDIO version 3.0
including the new UHS-I modes:
 DS: Default speed up to 25MHz (3.3V signaling).
 HS: High speed up to 50MH (3.3V signaling).
 SDR12: SDR up to 25MHz (1.8V signaling).
 SDR25: SDR up to 50MHz (1.8V signaling).
 SDR50: SDR up to 100MHz (1.8V signaling).
 SDR104: SDR up to 208MHz (1.8V signaling).
 DDR50: DDR up to 50MHz (1.8V signaling).
T
he SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for
applications requiring an interrupt different from the one provided by SDIO interface. The
ability to force control of gated clocks from within the device is also provided.
The following three functions are supported:
 Function 0 Standard SDIO function (Max BlockSize / ByteCount = 32B)
 Function 1 Backplane Function to access the internal System On Chip (SOC)
address space (Max BlockSize / ByteCount = 64B)
 Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max
BlockSize/ByteCount=512B)
SDIO Pin Description
SD 4-Bit Mode
DATA0 Data Line 0
DATA1 Data Line 1 or Interrupt
DATA2 Data Line 2 or Read Wait
DATA3 Data Line 3
CLK Clock
CMD Command Line