System User Guide / Owners Manual

10
nelstatusmarked“noreference”.Uponlossoflock,theoutputfrequencywillbe
heldconstant,seecase4.
2.AES3only.Uponselectionofslavemode,theCC1selectstheAES3input.The
“aes”dipswitchattherearselectswhethertheaudiodataistransmitted(thru)or
not(mute).Inthrumode,theAES3outputwillobviouslyrunatthesamemultipleas
theAES3input.Inmutemodeitwillbesynchronoustogroup2,audioisblackand
marked“noreference”.Uponlossoflocktheoutputratewillbeheldconstant,see
case4.The“AESlock”lightontherearwillbeonaslongastheCC1PLLislocked.
3.BothAES3andwordsyncarepresent.Wordsyncwilltakeprecedenceoverthe
AES3input.In“thru”modetheAES3outputwillproduceajitter-freecopyofthe
AES3input,providedtheinputsignalissynchronous.In“mute”modetheAES3
inputwillbeignoredaltogether.UponlossoftheAES3inputtheAES3outputwill
reverttoblack.Uponlossofthewordsyncinputtheoutputfrequencywillbeheld
constant(within1ppmofthelastdetectedfrequency)andthefrontslavelightwill
blinktoindicateanerror.Thefaultconditionisclearedeitherbyreattachingthe
wordsyncorbycyclingthesourceselectorthroughthetwomastermodesbackto
slavemodetoforcetheCC1tolocktotheAES3signalinstead.TheCC1willnever
automaticallyswitchfromwordsynctoAES3topreventclockloops.
4.NovalidsignaloneitherwordsyncorAES3input.Theresponseisnowdeter-
minedbythedipswitchnamed“unlock”.Whensetto“thru”,theclockfrequencywill
beheldconstantwithin1ppmofthelastvalidmeasuredfrequency.Whensetto
“mute”,theoutputswillbemuted.Inbothcasestheslavelightwillblinktoindicate
anerror.The“mute”modeisadvantageousatforinstancepostproductionwhere
theclockusuallyisoutofsightinamachineroom.Uponlossoflock,allclocksdis-
appearandyoursoftwareautomaticallyprovidesawarning.The“thru”modehasan
advantageinforinstanceliverecordingorPublicAddress.Heresoundshouldnever
mute,whateverhappens.
Lock indication
TheCC1detectswhethertheinputsignalisamultipleof44.1kHzor48kHz,and
indicatesthisontheLEDsabovethesourcepushbutton.Thefrequencymultiple
settingsofgroups1and2remainassetbytheuser.WhiletheCC1acquireslock,
theslavelightwillblink.Thiscantakeupto20s,onaccountoftheCC1’sextremely
slowPLLdesign(seechapter6,“JitterandPLL’sexplained”).Oncefrequencylock
isachieved,theslaveLEDwillcomeoncontinuously.ThePLLwillthensettleto0º
phaselockwiththeinputinanevenslowermode.Thesmallestachievablephase
errordependsmostlyonthestabilityoftheincomingclock.Thestatic(average)
phaseerrorisfactory-alignedtowithin50ns.