Data Sheet

ManualsBrandsGravitech ManualsArduinoArduino Nano USB Microcontroller v3

Table Of Contents

Features
1. Pin Configurations
- 1.1 Pin Descriptions
2. Overview
- 2.1 Block Diagram
- 2.2 Comparison Between ATmega48, ATmega88, and ATmega168
3. Resources
4. About Code Examples
5. AVR CPU Core
- 5.1 Overview
- 5.2 Architectural Overview
- 5.3 ALU - Arithmetic Logic Unit
- 5.4 Status Register
  - 5.4.1 SREG - AVR Status Register
- 5.5 General Purpose Register File
  - 5.5.1 The X-register, Y-register, and Z-register
- 5.6 Stack Pointer
  - 5.6.1 SPH and SPL - Stack Pointer High and Stack Pointer Low Register
- 5.7 Instruction Execution Timing
- 5.8 Reset and Interrupt Handling
  - 5.8.1 Interrupt Response Time
6. AVR Memories
- 6.1 Overview
- 6.2 In-System Reprogrammable Flash Program Memory
- 6.3 SRAM Data Memory
  - 6.3.1 Data Memory Access Times
- 6.4 EEPROM Data Memory
  - 6.4.1 EEPROM Read/Write Access
  - 6.4.2 Preventing EEPROM Corruption
- 6.5 I/O Memory
  - 6.5.1 General Purpose I/O Registers
- 6.6 Register Description
7. System Clock and Clock Options
- 7.1 Clock Systems and their Distribution
- 7.2 Clock Sources
  - 7.2.1 Default Clock Source
  - 7.2.2 Clock Startup Sequence
- 7.3 Low Power Crystal Oscillator
- 7.4 Full Swing Crystal Oscillator
- 7.5 Low Frequency Crystal Oscillator
- 7.6 Calibrated Internal RC Oscillator
- 7.7 128 kHz Internal Oscillator
- 7.8 External Clock
- 7.9 Clock Output Buffer
- 7.10 Timer/Counter Oscillator
- 7.11 System Clock Prescaler
- 7.12 Register Description
  - 7.12.1 OSCCAL - Oscillator Calibration Register
  - 7.12.2 CLKPR - Clock Prescale Register
8. Power Management and Sleep Modes
- 8.1 Sleep Modes
- 8.2 Idle Mode
- 8.3 ADC Noise Reduction Mode
- 8.4 Power-down Mode
- 8.5 Power-save Mode
- 8.6 Standby Mode
- 8.7 Power Reduction Register
- 8.8 Minimizing Power Consumption
- 8.9 Register Description
  - 8.9.1 SMCR - Sleep Mode Control Register
  - 8.9.2 PRR - Power Reduction Register
9. System Control and Reset
- 9.1 Resetting the AVR
- 9.2 Reset Sources
- 9.3 Power-on Reset
- 9.4 External Reset
- 9.5 Brown-out Detection
- 9.6 Watchdog System Reset
- 9.7 Internal Voltage Reference
  - 9.7.1 Voltage Reference Enable Signals and Start-up Time
- 9.8 Watchdog Timer
  - 9.8.1 Features
- 9.9 Register Description
  - 9.9.1 MCUSR - MCU Status Register
  - 9.9.2 WDTCSR - Watchdog Timer Control Register
10. Interrupts
- 10.1 Overview
- 10.2 Interrupt Vectors in ATmega48
- 10.3 Interrupt Vectors in ATmega88
- 10.4 Interrupt Vectors in ATmega168
  - 10.4.1 Moving Interrupts Between Application and Boot Space, ATmega88 and ATmega168
- 10.5 Register Description
  - 10.5.1 MCUCR - MCU Control Register
11. External Interrupts
- 11.1 Pin Change Interrupt Timing
- 11.2 Register Description
12. I/O-Ports
- 12.1 Overview
- 12.2 Ports as General Digital I/O
- 12.3 Alternate Port Functions
- 12.4 Register Description
13. 8-bit Timer/Counter0 with PWM
- 13.1 Features
- 13.2 Overview
  - 13.2.1 Definitions
  - 13.2.2 Registers
- 13.3 Timer/Counter Clock Sources
- 13.4 Counter Unit
- 13.5 Output Compare Unit
- 13.6 Compare Match Output Unit
  - 13.6.1 Compare Output Mode and Waveform Generation
- 13.7 Modes of Operation
- 13.8 Timer/Counter Timing Diagrams
- 13.9 Register Description
14. 16-bit Timer/Counter1 with PWM
- 14.1 Features
- 14.2 Overview
  - 14.2.1 Registers
  - 14.2.2 Definitions
- 14.3 Accessing 16-bit Registers
  - 14.3.1 Reusing the Temporary High Byte Register
- 14.4 Timer/Counter Clock Sources
- 14.5 Counter Unit
- 14.6 Input Capture Unit
- 14.7 Output Compare Units
- 14.8 Compare Match Output Unit
  - 14.8.1 Compare Output Mode and Waveform Generation
- 14.9 Modes of Operation
- 14.10 Timer/Counter Timing Diagrams
- 14.11 Register Description
15. Timer/Counter0 and Timer/Counter1 Prescalers
- 15.0.1 Internal Clock Source
- 15.0.2 Prescaler Reset
- 15.0.3 External Clock Source
- 15.1 Register Description
  - 15.1.1 GTCCR - General Timer/Counter Control Register
16. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 16.1 Features
- 16.2 Overview
  - 16.2.1 Registers
  - 16.2.2 Definitions
- 16.3 Timer/Counter Clock Sources
- 16.4 Counter Unit
- 16.5 Output Compare Unit
- 16.6 Compare Match Output Unit
  - 16.6.1 Compare Output Mode and Waveform Generation
- 16.7 Modes of Operation
- 16.8 Timer/Counter Timing Diagrams
- 16.9 Asynchronous Operation of Timer/Counter2
- 16.10 Timer/Counter Prescaler
- 16.11 Register Description
17. SPI - Serial Peripheral Interface
- 17.1 Features
- 17.2 Overview
- 17.3 SS Pin Functionality
  - 17.3.1 Slave Mode
  - 17.3.2 Master Mode
- 17.4 Data Modes
- 17.5 Register Description
18. USART0
- 18.1 Features
- 18.2 Overview
- 18.3 Clock Generation
- 18.4 Frame Formats
  - 18.4.1 Parity Bit Calculation
- 18.5 USART Initialization
- 18.6 Data Transmission - The USART Transmitter
- 18.7 Data Reception - The USART Receiver
- 18.8 Asynchronous Data Reception
- 18.9 Multi-processor Communication Mode
  - 18.9.1 Using MPCMn
- 18.10 Register Description
- 18.11 Examples of Baud Rate Setting
19. USART in SPI Mode
- 19.1 Features
- 19.2 Overview
- 19.3 Clock Generation
- 19.4 SPI Data Modes and Timing
- 19.5 Frame Formats
  - 19.5.1 USART MSPIM Initialization
- 19.6 Data Transfer
  - 19.6.1 Transmitter and Receiver Flags and Interrupts
  - 19.6.2 Disabling the Transmitter or Receiver
- 19.7 AVR USART MSPIM vs. AVR SPI
- 19.8 Register Description
20. 2-wire Serial Interface
- 20.1 Features
- 20.2 2-wire Serial Interface Bus Definition
  - 20.2.1 TWI Terminology
  - 20.2.2 Electrical Interconnection
- 20.3 Data Transfer and Frame Format
- 20.4 Multi-master Bus Systems, Arbitration and Synchronization
- 20.5 Overview of the TWI Module
- 20.6 Using the TWI
- 20.7 Transmission Modes
- 20.8 Multi-master Systems and Arbitration
- 20.9 Register Description
21. Analog Comparator
- 21.1 Overview
- 21.2 Analog Comparator Multiplexed Input
- 21.3 Register Description
22. Analog-to-Digital Converter
- 22.1 Features
- 22.2 Overview
- 22.3 Starting a Conversion
- 22.4 Prescaling and Conversion Timing
- 22.5 Changing Channel or Reference Selection
  - 22.5.1 ADC Input Channels
  - 22.5.2 ADC Voltage Reference
- 22.6 ADC Noise Canceler
- 22.7 ADC Conversion Result
- 22.8 Register Description
23. debugWIRE On-chip Debug System
- 23.1 Features
- 23.2 Overview
- 23.3 Physical Interface
- 23.4 Software Break Points
- 23.5 Limitations of debugWIRE
- 23.6 Register Description
  - 23.6.1 DWDR - debugWire Data Register
24. Self-Programming the Flash, ATmega48
- 24.1 Overview
- 24.2 Addressing the Flash During Self-Programming
- 24.3 Register Description
  - 24.3.1 SPMCSR - Store Program Memory Control and Status Register
25. Boot Loader Support - Read-While-Write Self-Programming, ATmega88 and ATmega168
- 25.1 Features
- 25.2 Overview
- 25.3 Application and Boot Loader Flash Sections
  - 25.3.1 Application Section
  - 25.3.2 BLS - Boot Loader Section
- 25.4 Read-While-Write and No Read-While-Write Flash Sections
  - 25.4.1 RWW - Read-While-Write Section
  - 25.4.2 NRWW - No Read-While-Write Section
- 25.5 Boot Loader Lock Bits
- 25.6 Entering the Boot Loader Program
- 25.7 Addressing the Flash During Self-Programming
- 25.8 Self-Programming the Flash
- 25.9 Register Description
  - 25.9.1 SPMCSR - Store Program Memory Control and Status Register
26. Memory Programming
- 26.1 Program And Data Memory Lock Bits
- 26.2 Fuse Bits
  - 26.2.1 Latching of Fuses
- 26.3 Signature Bytes
- 26.4 Calibration Byte
- 26.5 Page Size
- 26.6 Parallel Programming Parameters, Pin Mapping, and Commands
  - 26.6.1 Signal Names
- 26.7 Parallel Programming
- 26.8 Serial Downloading
27. Electrical Characteristics
- 27.1 Absolute Maximum Ratings*
- 27.2 DC Characteristics ATmega48/88/168*
- 27.3 Speed Grades
- 27.4 Clock Characteristics
- 27.5 System and Reset Characteristics
- 27.6 2-wire Serial Interface Characteristics
- 27.7 SPI Timing Characteristics
- 27.8 ADC Characteristics - Preliminary Data
- 27.9 Parallel Programming Characteristics
28. Typical Characteristics - Preliminary Data
- 28.1 Active Supply Current
- 28.2 Idle Supply Current
- 28.3 Supply Current of I/O modules
- 28.4 Power-Down Supply Current
- 28.5 Power-Save Supply Current
- 28.6 Standby Supply Current
- 28.7 Pin Pull-up
- 28.8 Pin Driver Strength
- 28.9 Pin Thresholds and Hysteresis
- 28.10 BOD Thresholds and Analog Comparator Offset
- 28.11 Internal Oscillator Speed
- 28.12 Current Consumption of Peripheral Units
- 28.13 Current Consumption in Reset and Reset Pulse width
29. Register Summary
30. Instruction Set Summary
31. Ordering Information
- 31.1 ATmega48
- 31.2 ATmega88
- 31.3 ATmega168
32. Packaging Information
- 32.1 32A
- 32.2 28M1
- 32.3 32M1-A
- 32.4 28P3
33. Errata
- 33.1 Errata ATmega48
- 33.2 Errata ATmega88
- 33.3 Errata ATmega168
34. Datasheet Revision History
- 34.1 Rev. 2545K-04/07
- 34.2 Rev. 2545J-12/06
- 34.3 Rev. 2545I-11/06
- 34.4 Rev. 2545H-10/06
- 34.5 Rev. 2545G-06/06
- 34.6 Rev. 2545F-05/05
- 34.7 Rev. 2545E-02/05
- 34.8 Rev. 2545D-07/04
- 34.9 Rev. 2545C-04/04
- 34.10 Rev. 2545B-01/04
Table of Contents

2545K–AVR–04/07

ATmega48/88/168

PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source.

• ADC0/PCINT8 – Port C, Bit 0

PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog

power.

PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source.

Table 12-7 and Table 12-8 relate the alternate functions of Port C to the overriding signals

shown in Figure 12-5 on page 76.

Note: 1. When enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4

and PC5. This is not shown in the figure. In addition, spike filters are connected between the

AIO outputs shown in the port figure and the digital logic of the TWI module.

Table 12-7. Overriding Signals for Alternate Functions in PC6..PC4

(1)

Signal

Name PC6/RESET

/PCINT14 PC5/SCL/ADC5/PCINT13 PC4/SDA/ADC4/PCINT12

PUOE RSTDISBL TWEN TWEN

PUOV 1 PORTC5 • PUD

PORTC4 • PUD

DDOE RSTDISBL TWEN TWEN

DDOV 0 SCL_OUT SDA_OUT

PVOE 0 TWEN TWEN

PVOV 0 0 0

DIEOE

RSTDISBL + PCINT14 •

PCIE1

PCINT13 • PCIE1 + ADC5D PCINT12 • PCIE1 + ADC4D

DIEOV RSTDISBL PCINT13 • PCIE1 PCINT12 • PCIE1

DI PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT

AIO RESET INPUT ADC5 INPUT / SCL INPUT ADC4 INPUT / SDA INPUT

Table 12-8. Overriding Signals for Alternate Functions in PC3..PC0

Signal

Name

PC3/ADC3/

PCINT11

PC2/ADC2/

PCINT10

PC1/ADC1/

PCINT9

PC0/ADC0/

PCINT8

PUOE0000

PUOV0000

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE0000

PVOV0000

DIEOE

PCINT11 • PCIE1 +

ADC3D

PCINT10 • PCIE1 +

ADC2D

PCINT9 • PCIE1 +

ADC1D

PCINT8 • PCIE1 +

ADC0D

DIEOV PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 PCINT8 • PCIE1

DI PCINT11 INPUT PCINT10 INPUT PCINT9 INPUT PCINT8 INPUT

AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT