Data Sheet

299
2545K–AVR–04/07
ATmega48/88/168
26.8.1 Serial Programming Pin Mapping
26.8.2 Serial Programming Algorithm
When writing serial data to the ATmega48/88/168, data is clocked on the rising edge of SCK.
When reading data from the ATmega48/88/168, data is clocked on the falling edge of SCK. See
Figure 26-9 for timing details.
To program and verify the ATmega48/88/168 in the serial programming mode, the following
sequence is recommended (See Serial Programming Instruction set in Table 26-17 on page
300):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET
must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchro-
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET
a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of
the address. If polling (RDY/BSY
) is not used, the user must wait at least t
WD_FLASH
before
issuing the next page (See Table 26-16). Accessing the serial programming interface
before the Flash write operation completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling (RDY/BSY
) is not used, the
user must wait at least t
WD_EEPROM
before issuing the next byte (See Table 26-16). In a
chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 6 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY
) is
not used, the used must wait at least t
WD_EEPROM
before issuing the next byte (See Table
26-16). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
Table 26-15. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB3 I Serial Data in
MISO PB4 O Serial Data out
SCK PB5 I Serial Clock