User Guide

GM500-U1G_A

Hardware Development Guide

EPHY_INT_N

EPHY_RST_N

SGMII_MDIO_CLK

SGMII_MDIO_DATA

SGMII_RX_P

SGMII_RX_M

SGMII_TX_P

SGMII_TX_M

Module

INT

SDN

SIP

SIN

RST_N

MDIO

MDC

SOP

VREF_1V8

10K

1.5K

0.1uF

AR8033

VREF_L5

0.1uF

Figure 2–36 SGMII + AR8033typical connection

NOTE:

1) Route SGMII differential signals with a controlled impedance of 100 Ω;

2) Keep SGMII away from other sensitive signals such as analog circuits, RF circuits, audio signals, etc., and

away from noise sources such as DCDC and clock signals;

3) SGMII intrapair length match<0.5mm;

4) TX to RX lane spacing and SGMII to all other signals spacing 3x line width.