User Guide

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47
GM500-U1G_A
Hardware Development Guide
ADC3 0.3 VBAT 1/3 1M 100 nA
Table 2-20ADC interface features(x1 scaling)
Item VIN Min(V) VIN Max(V) ADC channel
configuration
Minimum input
resistance(MΩ)
Maximum
input current
ADC1 0.1 1.7 1 10M 100 nA
ADC2 0.1 1.7 1 10M 100 nA
ADC3 0.1 1.7 1 10M 100 nA
NOTE:
ADC input voltage should not exceed VBAT;
The internal reference voltage of ADC is 1.8V;
When VBAT is not supplied, ADC1, ADC2 and ADC3 are forbidden to input current greater than 1uA.
2.14. WAKEUP_IN Signal
The module provides an AP control interface for communicating with external Application Processor including WAKEUP_IN. The
following table shows the pin definition of AP control interface.
Table 2-21 Pin Definition of WAKEUP_IN
Pin Name Pin NO. I/O Description Comment
WAKEUP_IN 72 DI Input control signal 1.8V power domain. Pull-down internally. Edge-triggered, Rising
edgewake up module; Falling edge modules can enter sleep.
If use this signal, please add a pull-up resistor externally.
When the module needs to be waken up, input a related signal via WAKEUP-IN. The following figure is the signal waveform:
WAKEUP_IN：
High
Low
Module state：
Module can
enter Sleep
Wake up state
High
Wake up state
Figure 2–30 WAKEUP_IN input sequence