User manual

LABKON Series
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GMC-I Messtechnik GmbH 45
The standard event register is cleared when:
1. You execute the *CLS (clear status) command.
2. You query the event register using the *ESR? (Event Status register) command.
For example, if 28 (4 + 8 + 16) is returned when you query the status of the standard event register, it is certain that QYE,
DDE, and EXE conditions have occurred.
The standard event enable register is cleared when:
1. You execute the *ESE 0 command.
2. You turn on the power and have configured the power supply using the *PSC 1 command.
3. The enable register will not be cleared at power-on if you have configured the power supply with the *PSC 0 command.
For example, you must send *ESE 24 (8 + 16) to enable DDE and EXE bits.
4.38 The Status Byte Register
The status byte summary register reports conditions from the other status registers. Query data that is waiting in the power
supply’s output buffer is immediately reported through the “Message Available” bit (bit 4) of status byte register. Bits in the
summary register are not latched. Clearing an event register will clear the corresponding bits in the status byte summary
register. Reading all messages in the output buffer, including any pending queries, will clear the message available bit.
Bit Definitions - Status Byte Summary Register
Bit
Decimal Value
Definition
0-2 not used
0
Always set to 0
3 QUES
8
One or more bits are set in the status register.
4 MAV
16
Data is available in the power supply’s output buffer.
5 ESB
32
One or more bits are stored in the standard event
register.
6 RQS
64
The power supply is requesting service (serial poll).
7 not used
0
Always set to 0
The status byte summary register is cleared when:
1. You execute the *CLS (clear status) command.
2. Querying the standard event register (*ESR? command) will clear only bit 5 in the status byte summary register.
For example, if 24 (8 + 16) is returned when you query the status of the Status Byte register, it is convinced that QUES and
MAV conditions have occurred.
The status byte enable register (Request Service) is cleared when:
1. You execute the *SRE 0 command.
2. You turn on the power and have configured the power supply using the *PSC 1 command.
3. The enable register will not be cleared at power-on if you have configured the power supply using *PSC 0.
For example, you must send *SRE 96 (32 + 64) to enable ESB and RQS bits.