User's Manual
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Quick reference data
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Limiting values
- 8. Recommended operating conditions
- 9. Thermal characteristics
- 10. Characteristics
- 10.1 Power management characteristics
- 10.2 Antenna presence self test thresholds
- 10.3 Typical 27.12 MHz Crystal requirements
- 10.4 Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)
- 10.5 RSTPD_N input pin characteristics
- 10.6 Input pin characteristics for I0, I1 and TESTEN
- 10.7 RSTOUT_N output pin characteristics
- 10.8 Input/output characteristics for pin P70_IRQ
- 10.9 Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX, P32_INT0, P33_INT1
- 10.10 Input/output pin characteristics for P35
- 10.11 Input/output pin characteristics for DP and DM
- 10.12 Input pin characteristics for SCL
- 10.13 Input/output pin characteristics for SDA
- 10.14 Output pin characteristics for DELATT
- 10.15 Input pin characteristics for SIGIN
- 10.16 Output pin characteristics for SIGOUT
- 10.17 Input/output pin characteristics for P34
- 10.18 Output pin characteristics for LOADMOD
- 10.19 Input pin characteristics for RX
- 10.20 Output pin characteristics for AUX1/AUX2
- 10.21 Output pin characteristics for TX1/TX2
- 10.22 System reset timing
- 10.23 Timing for the I2C-bus interface
- 10.24 Temperature sensor
- 11. Application information
- 12. Abbreviations
- 13. Revision history
- 14. Legal information
- 15. Contact information
- 16. Tables
- 17. Figures
- 18. Contents
PR533_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436 5 of 36
NXP Semiconductors
PR533
USB NFC integrated reader solution
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration for HVQFN 40 (SOT618-1)
aaa-000044
PR533
P70_IRQ
VMID
RX
RSTOUT_N
AVDD DVSS
TVSS2 DM
TX2 DP
TVDD PVDD
TX1 DELATT
TVSS1 P30
LOADMOD P31
DVSS P32_INT0
AVSS
AUX1
AUX2
DVSS
OSCIN
OSCOUT
I0
I1
TESTEN
P35
VBUS
DVDD
RSTPD_N
SVDD
SIGIN
SIGOUT
P34
SDA
P50_SCL
P33_INT1
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
terminal 1
index area
Transparent top view
Table 3. PR533 pin description
Symbol Pin Type Pad ref
voltage
Description
DVSS 1 G digital ground
LOADMOD 2 O DVDD load modulation output provides digital signal for FeliCa and MIFARE card
operating mode
TVSS1 3 G transmitter ground: supplies the output stage of TX1
TX1 4 O TVDD transmitter 1: transmits modulated 13.56 MHz energy carrier
TVDD 5 P transmitter power supply: supplies the output stage of TX1 and TX2
TX2 6 O TVDD transmitter 2: delivers the modulated 13.56 MHz energy carrier
TVSS2 7 G transmitter ground: supplies the output stage of TX2
AVDD 8 P analog power supply
VMID 9 P AVDD internal reference voltage: This pin delivers the internal reference voltage.
RX 10 I AVDD receiver input: Input pin for the reception signal, which is the load modulated
13.56 MHz energy carrier from the antenna circuit
AVSS 11 G analog ground
AUX1 12 O DVDD auxiliary output 1: This pin delivers analog and digital test signals
AUX2 13 O DVDD auxiliary output 2: This pin delivers analog and digital test signals
DVSS 14 G digital ground