User's Manual

PR533_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436 4 of 36
NXP Semiconductors
PR533
USB NFC integrated reader solution
4. Ordering information
[1] 60 or 70 refers to the ROM code version described in the User Manual. For differences of romcode versions refer to the release note of
the product.
[2] Refer to Section 14.4 “
Licenses”.
[3] MSL 2 (Moisture Sensitivity Level).
5. Block diagram
The following block diagram describes hardware blocks controlled by PR5331C3HN
firmware or which can be accessible for data transaction by a host baseband.
Table 2. Ordering information
Type number Package
Name Description Version
PR5331C3HN/C360
[1][2][3]
HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6  6  0.85 mm
SOT618-1
PR5331C3HN/C370
[1][2][3]
Fig 1. Block diagram
aaa-000043
SUPPLY
SUPERVISOR
27 MHz OSC
AND
FRAC N
PLL
SVDD
SWITCH
NFC
ANALOG
FRONT END
AND
CLUART
80C51 CPU
44 k ROM
1.2 k BYTES RAM
USB
DEVICE
I
2
C
MASTER
MATX
RSTPD_N
PVDD
SVDD
VBUS
P30 P31 P32_INT0
GPIOs
P33_INT0 P35
RSTOUT_N DVDD P70_IRQ AVSS
DVSS
OSCIN
OSCOUT
I0
I1
SDA
P50_SCL
DELATT
48 MHz
SIGIN
SIGOUT
P34
TVDD
AVDD
RX
VMID
TX1
TVSS
TX2
REGULATOR
3.3 V
PCR