User's Manual

PR533_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436 27 of 36
NXP Semiconductors
PR533
USB NFC integrated reader solution
10.23 Timing for the I
2
C-bus interface
[1] The PR533 has a slope control according to the I
2
C-bus specification for the Fast mode. The slope control
is always present and not dependent of the I
2
C-bus speed.
[2] 27.12 MHz quartz starts in less than 800 s. For example, quartz like TAS-3225A, TAS-7 or KSS2F with
appropriate layout.
[3] The PR533 has an internal hold time of around 270 ns for the SDA signal to bridge the undefined region of
the falling edge of P50_SCL.
Fig 7. I
2
C-bus parameters
Table 35. I
2
C-bus timing specification
Symbol Parameter Conditions Min Typ Max Unit
f
SCL
SCL clock frequency 0 - 400 kHz
t
HD;STA
hold time (repeated) START condi-
tion
after this period, the
first clock pulse is
generated
600 - - ns
t
SU;STA
set-up time for a repeated START
condition
600 - - ns
t
SU;STO
set-up time for STOP condition 600 - - ns
t
LOW
LOW period of the SCL clock P50_SCL 1300 - - ns
t
HIGH
HIGH period of the SCL clock P50_SCL 600 - - ns
t
HD;DAT
data hold time 0 - 900 ns
t
SU;DAT
data set-up time 100 - - ns
t
r
rise time of both SDA and SCL sig-
nals
P50_SCL
[1]
20 - 300 ns
t
f
fall time of both SDA and SCL sig-
nals
P50_SCL
[1]
20 - 300 ns
t
BUF
bus free time between a STOP
and START condition
1.3 - - ms
t
stretch
stretch time stretching time on
P50_SCL when
woken-up on its
own address
[2]
--1ms
t
h
hold time internal for SDA 330 - 590 ns
internal for SDA in
SPD mode
[3]
-270-ns
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SDA
t
f
SCL
t
LOW
t
f
t
SP
t
r
t
HD;STA
t
HD;DAT
t
HD;STA
t
r
t
HIGH
t
SU;DAT
SSrPS
t
SU;STA
t
SU;STO
t
BUF