User's Manual

Table Of Contents

WriteMode

CKPH – 1,CKPL – 0(MSP430)

Data Transition – SCLKFallingEdge

MOSIValid – SCLKRisingEdge

Switch

SCLK

Polarity

ReadMode

CKPH – 0,CKPL – 0(MSP430)

Data Transition – SCLKRisingEdge

MISOValid – SCLKFallingEdge

SingleReadOperation

SCLK

MOSI

MISO

SS*

Write AddressByte ReadDataByte

Don'tCare

NoData Transitions(AllHigh/Low)

TRF7960

TRF7961

SLOU186F–AUGUST 2006–REVISED AUGUST 2010

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The SPI read operation is shown in Figure 5-10.

Figure 5-10. Serial – SPI Interface Communication (Read Mode)

The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data

changes on the falling edge, and is validated in the reader on the rising edge, as shown in Figure 5-10.

During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is

validated at the eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO

pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first).

Note:

When using the hardware SPI (for example, an MSP430 hardware SPI) to implement the foregoing

feature, care must be taken to switch the SCLK polarity after write phase for proper read operation.

The example clock polarity for the MSP430-specific environment is shown in the write-mode and

read-mode boxes of Figure 5-10. See the USART-SPI chapter for any specific microcontroller family

for further information on the setting the appropriate clock polarity.

This clock polarity switch must be done for all read (single, continuous) operations.

The MOSI (serial data out) should not have any transitions (all high or all low) during the read cycle. Also,

the SS* should be low during the whole write and read operation.

The continuous read operation is illustrated in Figure 5-11

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