User's Manual
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Description (continued)
- 3 Physical Characteristics
- 4 ELECTRICAL SPECIFICATIONS
- 5 System Description
- 5.1 Power Supplies
- 5.2 Receiver – Analog Section
- 5.3 Register Descriptions
- 5.4 Direct Commands From MCU to Reader
- 5.4.1 Command Codes
- 5.4.2 Reset
- 5.4.3 Transmission With CRC
- 5.4.4 Transmission Without CRC
- 5.4.5 Delayed Transmission With CRC
- 5.4.6 Delayed Transmission Without CRC
- 5.4.7 Transmission Next Slot
- 5.4.8 Receiver Gain Adjust
- 5.4.9 Test External RF (RSSI at RX input with TX OFF)
- 5.4.10 Test Internal RF (RSSI at RX input with TX ON)
- 5.4.11 Block Receiver
- 5.4.12 Enable Receiver
- 5.5 Reader Communication Interface
- 5.6 Parallel Interface Communication
- 5.7 Serial Interface Communication
- 5.8 External Power Amplifier Application
TRF7960
TRF7961
www.ti.com
SLOU186F–AUGUST 2006–REVISED AUGUST 2010
5.3.4 FIFO Control Registers
Table 5-26. FIFO Status (1Ch)
Low nibbles of complete bytes to be transferred through FIFO; Information about a broken byte and number of bits to be transferred from it
Bit Bit Name Function Comments
B7 RFU Set to LOW Reserved for future use (RFU)
B6 Fhil FIFO level HIGH Indicates that 9 bytes are already in the FIFO (for RX)
B5 Flol FIFO level LOW Indicates that only 3 bytes are in the FIFO (for TX)
B4 Fove FIFO overflow error Too much data was written to the FIFO
B3 Fb3 FIFO bytes fb[3] Bits B0:B3 indicate how many bytes that are loaded in FIFO were not read
out yet (displays N – 1 number of bytes). If 8 bytes are in the FIFO, this
number is 7.
B2 Fb2 FIFO bytes fb[2]
B1 Fb1 FIFO bytes fb[1]
B0 Fb0 FIFO bytes fb[0]
Table 5-27. TX Length Byte1 (1Dh)
High 2 nibbles of complete bytes to be transferred through FIFO
Register default is set to 0x00 at POR and EN=0. It is also automatically reset at TX EOF
Bit Bit Name Function Comments
B7 Txl11 Number of complete byte bn[11] High nibble of complete bytes to be transmitted
B6 Txl10 Number of complete byte bn[10]
B5 Txl9 Number of complete byte bn[9]
B4 Txl8 Number of complete byte bn[8]
B3 Txl7 Number of complete byte bn[7] Middle nibble of complete bytes to be transmitted
B2 Txl6 Number of complete byte bn[6]
B1 Txl5 Number of complete byte bn[5]
B0 Txl4 Number of complete byte bn[4]
Table 5-28. TX Length Byte2 (1Eh)
Low nibbles of complete bytes to be transferred through FIFO; Information about a broken byte and number of bits to be transferred from it
Register default is set to 0x00 at POR and EN=0. It is also automatically reset at TX EOF
Bit Bit Name Function Comments
B7 Txl3 Number of complete byte bn[3] Low nibble of complete bytes to be transmitted
B6 Txl2 Number of complete byte bn[2]
B5 Txl1 Number of complete byte bn[1]
B4 Txl0 Number of complete byte bn[0]
B3 Bb2 Broken byte number of bits bb[2] Number of bits in the last broken byte to be transmitted.
B2 Bb1 Broken byte number of bits bb[1] It is taken into account only when broken byte flag is set.
B1 Bb0 Broken byte number of bits bb[0]
B0 Bbf Broken byte flag If 1, indicates that last byte is not complete 8 bits wide.
Copyright © 2006–2010, Texas Instruments Incorporated System Description 33
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