User's Manual
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Description (continued)
- 3 Physical Characteristics
- 4 ELECTRICAL SPECIFICATIONS
- 5 System Description
- 5.1 Power Supplies
- 5.2 Receiver – Analog Section
- 5.3 Register Descriptions
- 5.4 Direct Commands From MCU to Reader
- 5.4.1 Command Codes
- 5.4.2 Reset
- 5.4.3 Transmission With CRC
- 5.4.4 Transmission Without CRC
- 5.4.5 Delayed Transmission With CRC
- 5.4.6 Delayed Transmission Without CRC
- 5.4.7 Transmission Next Slot
- 5.4.8 Receiver Gain Adjust
- 5.4.9 Test External RF (RSSI at RX input with TX OFF)
- 5.4.10 Test Internal RF (RSSI at RX input with TX ON)
- 5.4.11 Block Receiver
- 5.4.12 Enable Receiver
- 5.5 Reader Communication Interface
- 5.6 Parallel Interface Communication
- 5.7 Serial Interface Communication
- 5.8 External Power Amplifier Application
TRF7960
TRF7961
www.ti.com
SLOU186F–AUGUST 2006–REVISED AUGUST 2010
5.3.2 Control Registers – Sub Level Configuration Registers
Table 5-12. ISO14443B TX Options (02h)
Selects the ISO subsets for ISO14443B – TX
Register default is set to 0x00 at POR = H or EN = L
Bit Bit Name Function Comments
B7 egt2 TX EGT time select MSB Three bit code defines the number of etu (0-7) which
separate two characters. ISO14443B TX only
B6 egt1 TX EGT time select
B5 egt0 TX EGT time select LSB
B4 eof_l0 1 = EOF, 0 length 11 etu ISO14443B TX only
0 = EOF, 0 length 10 etu
B3 sof_l1 1 = SOF, 1 length 03 etu
0 = SOF, 1 length 02 etu
B2 sof _l0 1 = SOF, 0 length 11 etu
0 = SOF, 0 length 10 etu
B1 l_egt 1 = EGT after each byte
0 = EGT after last byte is omitted
B0 Unused
Table 5-13. ISO 14443A High-Bit-Rate Options (03h)
Parity
Register default is set to 0x00 at POR = H, or EN = L and at each write to ISO control register
Bit Bit Name Function Comments
B7 dif_tx_br TX bit rate different than RX bit rate enable Valid for ISO14443A/B high bit rate
B6 tx_br1 TX bit rate tx_br1 = 0, tx_br = 0 106 kbps
tx_br1 = 0, tx_br = 1 212 kbps
B5 tx_br0
tx_br1 = 1, tx_br = 0 424 kbps
tx_br1 = 1, tx_br = 1 848 kbps
B4 parity-2tx 1 = parity odd except last byte which is even for TX For 14443A high bit rate, coding and decoding
B3 parity-2rx 1 = parity odd except last byte which is even for RX
B2 Unused
B1 Unused
B0 Unused
Table 5-14. TX Timer H-Byte (04h)
Register default is set to 0xC2 at POR = H or EN = L and at each write to ISO control register
Bit Bit Name Function Comments
B7 Tm_st1 Timer start condition tm_st1 = 0, tm_st0 = 0 beginning of TX SOF
tm_st1 = 0, tm_st0 = 1 end of TX SOF
B6 Tm_st0 Timer start condition
tm_st1 = 1, tm_st0 = 0 beginning of RX SOF
tm_st1 = 1, tm_st0 = 1 end of RX SOF
B5 Tm_lengthD Timer length MSB
B4 Tm_lengthC Timer length
B3 Tm_lengthB Timer length
B2 Tm_lengthA Timer length
B1 Tm_length9 Timer length
B0 Tm_length8 Timer length LSB
Copyright © 2006–2010, Texas Instruments Incorporated System Description 27
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