User's Manual
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Description (continued)
- 3 Physical Characteristics
- 4 ELECTRICAL SPECIFICATIONS
- 5 System Description
- 5.1 Power Supplies
- 5.2 Receiver – Analog Section
- 5.3 Register Descriptions
- 5.4 Direct Commands From MCU to Reader
- 5.4.1 Command Codes
- 5.4.2 Reset
- 5.4.3 Transmission With CRC
- 5.4.4 Transmission Without CRC
- 5.4.5 Delayed Transmission With CRC
- 5.4.6 Delayed Transmission Without CRC
- 5.4.7 Transmission Next Slot
- 5.4.8 Receiver Gain Adjust
- 5.4.9 Test External RF (RSSI at RX input with TX OFF)
- 5.4.10 Test Internal RF (RSSI at RX input with TX ON)
- 5.4.11 Block Receiver
- 5.4.12 Enable Receiver
- 5.5 Reader Communication Interface
- 5.6 Parallel Interface Communication
- 5.7 Serial Interface Communication
- 5.8 External Power Amplifier Application
Mode 2: Full ISO With Framing and Error Checking (Typical Mode)
AnalogFrontEnd(AFE)
Packetization/Framing
14443A 14443B 15693
Tag-it
ISOEncoder/Decoders
Mode0:
Raw,Sub-CarrierData
Mode1:
Un-FramedRawISO
FormattedData
TRF7960
TRF7961
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SLOU186F–AUGUST 2006–REVISED AUGUST 2010
Figure 5-4. User-Configurable Modes
5.2.5 Register Preset
After power-up and the EN pin low-to-high transition, the reader is in the default mode. The default
configuration is ISO15693, single sub-carrier, high data rate, 1-out-of-4 operation. The low-level option
registers (02…0B) are automatically set to adapt the circuitry optimally to the appropriate protocol
parameters.
When entering another protocol (writing to the ISO control register 01), the low-level option registers
(02…0B) are automatically configured to the new protocol parameters.
After selecting the protocol, it is possible to change some low-level register contents if needed. However,
changing to another protocol and then back, reloads the default settings, and the user must reload the
custom settings.
The Clo1 and Clo0 (register 09) bits, which define the microcontroller frequency available on the
SYS_CLK pin, are the only two bits in the configuration registers that are not cleared during protocol
selection.
Copyright © 2006–2010, Texas Instruments Incorporated System Description 23
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