User's Manual

apmcomm confidential
apm6658/6659 WiFi 802.11 b/g/n & BT2.1+EDR Dual Radio Module
Product Information Data Sheet
Page 8 of 30
apm Communication, Inc. – TEL: [phone] – FAX: [phone]
Website: http://www.apmcomm.com – E-mail:
[e-mail]
apmcomm Proprietary and Confidential – Product information is subject to change without notice.– May 30 2011
1-3-2 Pin Description
* I/O: Digital Input/Output, I: Digital Input, O: Digital Output, A: Analog, PU: Pull-up, PD: Pull-down
# Name
I/O
Pin Status
on Reset
Supply Domain Description
1 BT_PCM_IN
I
PD BT_VDD_PADS Synchronous data input
2 BT_PCM_OUT
O
PD BT_VDD_PADS Synchronous data output
3 WL_SPI_MISO
O
PD WL_VDD_PADS_0_7
Debug SPI data output
4 WL_SPI_CLK
I
PD WL_VDD_PADS_0_7
Debug SPI clock
5 WL_SPI_MOSI
I
PD WL_VDD_PADS_0_7
Debug SPI data input
6 WL_SPI_CSn
I
PU WL_VDD_PADS_0_7
Debug SPI chip select, active low
7 BT_CLK
I
- - Clock input for BT
8 WL_CLK
I
- - Clock input for WiFi
9 WL_PIO[9]
I/O
PD WL_3V3 Programmable input/output
10 BT_UART_CTS
I/O
PU BT_VDD_PADS UART clear to send, active low
11 BT_SD_CLK
I
PU BT_VDD_PADS SDIO Clock
12 BT_SD_CMD
I
PU BT_VDD_PADS SDIO data input
13 BT_SD_CSn
I
PU BT_VDD_PADS
SDIO chip select to allow SDIO
accesses
14 BT_UART_TX
O
PU BT_VDD_PADS
UART data output active high
15 BT_UART_RX
I
PU BT_VDD_PADS
UART data input active high
16 BT_UART_RTS
O
PU BT_VDD_PADS
UART request to send active low
17 BT_CLK32K
I
PD BT_VDD_PADS
Dedicated 32kHz external reference
clock input
18 BT_VDD_PADS
Power
- -
Positive supply for all digital
Input/Output ports,
UART/SDIO ports, and PIO ports
19 WL_1V8
Power
- -
Power supply for analogue/digital
sections
20 BT_PIO[4]
I/O
PD BT_VDD_PADS Programmable input/output
21 WL_VREG_EN
Power
PD - Take high to enable regulator
22 BT_PIO[2]
I/O
PD BT_VDD_PADS Programmable input/output
23 WL_VSDIO
Power
- -
Host interface digital I/O power
supply
24 WL_SD_DAT[2]
I/O
PU WL_VSDIO
SDIO 4-bit mode: Data line [bit 2] or
Read wait (optional)
SDIO 1-bit mode: Read Wait
(optional)
SDIO SPI mode: Reserved