User's Manual

apmcomm confidential
apm6658/6659 WiFi 802.11 b/g/n & BT2.1+EDR Dual Radio Module
Product Information Data Sheet
Page 17 of 30
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apmcomm Proprietary and Confidential – Product information is subject to change without notice.– May 30 2011
a nominal frequency. In either case the generated clock will be slower than in normal operation, but this is sufficient for
safely booting and configuring the IC.
Power-on Reset Min Typ Max Units
Reset release on WL_VDD_DIG rising (HI) 1.05 - 1.15 V
Reset assert on WL_VDD_DIG falling (LO)
HI-0.060
- HI-0.045 V
Reset assert on WL_VDD_DIG falling
(Sleep mode)
0.80
0.825 0.85 V
1-6-2 Bluetooth Reset
The BT_RESETB pin is an active low reset and is internally filtered using the internal low frequency clock
oscillator. A reset is performed between 1.5 and 4.0ms following BT_RESETB being active. It is recommended that
BT_RESET be applied for a period greater than 5ms.
The power on reset occurs when the BT_VDD_CORE supply falls below 1.24V and is released when
BT_VDD_CORE rises above typically 1.31V. At reset the digital I/O pins are set to input for bi-directional pins and
outputs are tri-state. Following a reset, BT assumes the maximum BT_CLK frequency, which ensures that the internal
clocks run at a safe (low) frequency until BT is configured for the actual BT_CLK frequency. If no clock is present at
BT_CLK, the oscillator in BT free runs, again at a safe frequency.
Power-on Reset Min Typ Max Units
BT_VDD_CORE Falling threshold 1.13 1.25 1.30 V
BT_VDD_CORE rising threshold
1.2
1.30 1.35 V
Hysteresis
0.05
0.10 0.15 V