User's Manual

TRF7970A
www.ti.com SLOS743K –AUGUST 2011–REVISED APRIL 2014
Table 6-44. IRQ Status Register (0x0C) for NFC and Card Emulation Operation
Function: Information available about TRF7970A IRQ and TX/RX status
Default: 0x00 at POR = H or EN = L, and at each write to the ISO Control Register 0x01. It is also automatically reset at the end of a read
phase. The reset also removes the IRQ flag.
Bit Name Function Description
Signals that TX is in progress. The flag is set at the start of TX but the interrupt
B7 Irq_tx IRQ set due to end of TX
request (IRQ = 1) is sent when TX is finished.
Signals that RX SOF was received and RX is in progress. The flag is set at the
B6 Irg_srx IRQ set due to RX start
start of RX but the interrupt request (IRQ = 1) is sent when RX is finished.
Signals FIFO high or low as set in the Adjustable FIFO IRQ Levels (0x14)
B5 Irq_fifo Signals the FIFO level
register
B4 Irq_err1 Protocol error Any protocol error
B3 Irq_sdd SDD completed SDD (passive target at 106 kbps) successfully finished
B2 Irq_rf RF field change Sufficient RF signal level for operation was reached or lost
RF collision avoidance The system has finished collision avoidance and the minimum wait time is
B1 Irq_col
finished elapsed.
RF collision avoidance not The external RF field was present so the collision avoidance could not be
B0 Irq_col_err
finished successfully carried out.
6.14.3.3.2 Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
Table 6-45. Interrupt Mask Register (0x0D)
Default: 0x3E at POR = H and EN = L. Collision bits reset automatically after read operation.
Bit Name Function Description
B7 Col9 Bit position of collision MSB Supports ISO14443A
B6 Col8 Bit position of collision
B5 En_irq_fifo Interrupt enable for FIFO Default = 1
B4 En_irq_err1 Interrupt enable for CRC Default = 1
B3 En_irq_err2 Interrupt enable for Parity Default = 1
Interrupt enable for Framing
B2 En_irq_err3 Default = 1
error or EOF
Interrupt enable for collision
B1 En_irq_col Default = 1
error
Enables no-response
B0 En_irq_noresp Default = 0
interrupt
Table 6-46. Collision Position Register (0x0E)
Function: Displays the bit position of collision or error
Default: 0x00 at POR = H and EN = L. Automatically reset after read operation.
Bit Name Function Description
B7 Col7 Bit position of collision MSB
B6 Col6
B5 Col5
B4 Col4
ISO14443A mainly supported, in the other protocols this register shows the bit
position of error. Either frame, SOF/EOF, parity or CRC error.
B3 Col3
B2 Col2
B1 Col1
B0 Col0 Bit position of collision LSB
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