User's Manual
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Characteristics
- 4 Terminal Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 6.1 Overview
- 6.2 System Block Diagram
- 6.3 Power Supplies
- 6.4 Receiver – Analog Section
- 6.5 Receiver – Digital Section
- 6.6 Oscillator Section
- 6.7 Transmitter – Analog Section
- 6.8 Transmitter – Digital Section
- 6.9 Transmitter – External Power Amplifier and Subcarrier Detector
- 6.10 TRF7970A IC Communication Interface
- 6.11 Special Direct Mode for Improved MIFARE Compatibility
- 6.12 NFC Modes
- 6.13 Direct Commands from MCU to Reader
- 6.13.1 Command Codes
- 6.13.1.1 Idle (0x00)
- 6.13.1.2 Software Initialization (0x03)
- 6.13.1.3 Initial RF Collision Avoidance (0x04)
- 6.13.1.4 Response RF Collision Avoidance (0x05)
- 6.13.1.5 Response RF Collision Avoidance (0x06, n = 0)
- 6.13.1.6 Reset (0x0F)
- 6.13.1.7 Transmission With CRC (0x11)
- 6.13.1.8 Transmission Without CRC (0x10)
- 6.13.1.9 Delayed Transmission With CRC (0x13)
- 6.13.1.10 Delayed Transmission Without CRC (0x12)
- 6.13.1.11 Transmit Next Time Slot (0x14)
- 6.13.1.12 Block Receiver (0x16)
- 6.13.1.13 Enable Receiver (0x17)
- 6.13.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
- 6.13.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
- 6.13.1.16 Receiver Gain Adjust (0x1A)
- 6.13.1 Command Codes
- 6.14 Register Description
- 7 Application Schematic and Layout Considerations
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
TRF7970A
www.ti.com
SLOS743K –AUGUST 2011–REVISED APRIL 2014
6.14.3.2.8 Modulator and SYS_CLK Control Register (0x09)
The frequency of SYS_CLK (pin 27) is programmable by the bits B4 and B5 of this register. The frequency
of the TRF7970A system clock oscillator is divided by 1, 2 or 4 resulting in available SYS_CLK
frequencies of 13.56 MHz or 6.78 MHz or 3.39 MHz.
The ASK modulation depth is controlled by bits B0, B1 and B2. The range of ASK modulation is 7% to
30% or 100% (OOK). The selection between ASK and OOK (100%) modulation can also be done using
direct input OOK (pin 12). The direct control of OOK/ASK using OOK pin is only possible if the function is
enabled by setting B6 = 1 (en_ook_p) in this register (0x09) and the ISO Control Register (0x01, B6 = 1).
When configured this way, the MOD (pin 14) is used as input for the modulation signal.
Table 6-36. Modulator and SYS_CLK Control Register (0x09)
Function: Controls the modulation input and depth, ASK / OOK control and clock output to external system (MCU)
Default: 0x91 at POR = H or EN = L, and at each write to ISO control register, except Clo1 and Clo0.
Bit Name Function Description
B7 27MHz Enables 27.12-MHz crystal Default = 1 (enabled)
Enable ASK/OOK pin (pin 12) for "on the fly change" between any preselected
1 = Enables external
ASK modulation as defined by B0 to B2 and OOK modulation:
selection of ASK or OOK
B6 en_ook_p modulation If B6 is 1, pin 12 is configured as follows:
0 = Default operation as
1 = OOK modulation
defined in B0 to B2 (0x09)
0 = Modulation as defined in B0 to B2 (0x09)
SYS_CLK Output SYS_CLK Output
Clo1 Clo0 (if 13.56-MHz (if 27.12-MHz
SYS_CLK output frequency
crystal is used) crystal is used)
B5 Clo1
MSB
0 0 Disabled Disabled
0 1 3.39 MHz 6.78 MHz
1 0 6.78 MHz 13.56 MHz
SYS_CLK output frequency
B4 Clo0
LSB
1 1 13.56 MHz 27.12 MHz
1 = Sets pin 12 (ASK/OOK)
For test and measurement purpose. ASK/OOK pin 12 can be used to monitor
B3 en_ana as an analog output
the analog subcarrier signal before the digitizing with DC level equal to AGND.
0 = Default
Pm2 Pm1 Pm0 Mod Type and %
B2 Pm2 Modulation depth MSB 0 0 0 ASK 10%
0 0 1 OOK (100%)
0 1 0 ASK 7%
B1 Pm1 Modulation depth 0 1 1 ASK 8.5%
1 0 0 ASK 13%
1 0 1 ASK 16%
B0 Pm0 Modulation depth LSB 1 1 0 ASK 22%
1 1 1 ASK 30%
Copyright © 2011–2014, Texas Instruments Incorporated Detailed Description 63
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