User's Manual

TRF7970A
www.ti.com SLOS743K –AUGUST 2011–REVISED APRIL 2014
6.13.1.16 Receiver Gain Adjust (0x1A)
This command should be executed when the MCU determines that no TAG response is coming and when
the RF and receivers are switched ON. When this command is received, the reader observes the digitized
receiver output. If more than two edges are observed in 100 ms, the window comparator voltage is
increased. The procedure is repeated until the number of edges (changes of logical state) of the digitized
reception signal is less than 2 (in 100 ms). The command can reduce the input sensitivity in 5-dB
increments up to 15 dB. This command ensures better operation in a noisy environment. The gain setting
is reset to maximum gain at EN = 0 and POR = 1.
6.14 Register Description
6.14.1 Register Preset
After power-up and the EN pin low-to-high transition, the reader is in the default mode. The default
configuration is ISO15693, single subcarrier, high data rate, 1-out-of-4 operation. The low-level option
registers (0x02 to 0x0B) are automatically set to adapt the circuitry optimally to the appropriate protocol
parameters. When entering another protocol (by writing to the ISO Control register 0x01), the low-level
option registers (0x02 to 0x0B) are automatically configured to the new protocol parameters. After
selecting the protocol, it is possible to change some low-level register contents if needed. However,
changing to another protocol and then back, reloads the default settings, and so then the custom settings
must be reloaded.
The Clo0 and Clo1 register (0x09) bits, which define the microcontroller frequency available on the
SYS_CLK pin, are the only two bits in the configuration registers that are not cleared during protocol
selection.
6.14.2 Register Overview
Table 6-24. Register Definitions
Address Register Read/Write
Main Control Registers
0x00 Chip Status Control R/W
0x01 ISO Control R/W
Protocol Sub-Setting Registers
0x02 ISO14443B TX options R/W
0x03 ISO14443A high bit rate options R/W
0x04 TX timer setting, H-byte R/W
0x05 TX timer setting, L-byte R/W
0x06 TX pulse-length control R/W
0x07 RX no response wait R/W
0x08 RX wait time R/W
0x09 Modulator and SYS_CLK control R/W
0x0A RX Special Setting R/W
0x0B Regulator and I/O control R/W
0x10 Special Function Register, Preset 0x00 R/W
0x11 Special Function Register, Preset 0x00 R/W
0x14 Adjustable FIFO IRQ Levels Register R/W
0x15 Reserved R/W
0x16 NFC Low Field Detection Level R/W
0x17 NFCID1 Number (up to 10 bytes wide) W
0x18 NFC Target Detection Level R/W
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