User's Manual
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Characteristics
- 4 Terminal Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 6.1 Overview
- 6.2 System Block Diagram
- 6.3 Power Supplies
- 6.4 Receiver – Analog Section
- 6.5 Receiver – Digital Section
- 6.6 Oscillator Section
- 6.7 Transmitter – Analog Section
- 6.8 Transmitter – Digital Section
- 6.9 Transmitter – External Power Amplifier and Subcarrier Detector
- 6.10 TRF7970A IC Communication Interface
- 6.11 Special Direct Mode for Improved MIFARE Compatibility
- 6.12 NFC Modes
- 6.13 Direct Commands from MCU to Reader
- 6.13.1 Command Codes
- 6.13.1.1 Idle (0x00)
- 6.13.1.2 Software Initialization (0x03)
- 6.13.1.3 Initial RF Collision Avoidance (0x04)
- 6.13.1.4 Response RF Collision Avoidance (0x05)
- 6.13.1.5 Response RF Collision Avoidance (0x06, n = 0)
- 6.13.1.6 Reset (0x0F)
- 6.13.1.7 Transmission With CRC (0x11)
- 6.13.1.8 Transmission Without CRC (0x10)
- 6.13.1.9 Delayed Transmission With CRC (0x13)
- 6.13.1.10 Delayed Transmission Without CRC (0x12)
- 6.13.1.11 Transmit Next Time Slot (0x14)
- 6.13.1.12 Block Receiver (0x16)
- 6.13.1.13 Enable Receiver (0x17)
- 6.13.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
- 6.13.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
- 6.13.1.16 Receiver Gain Adjust (0x1A)
- 6.13.1 Command Codes
- 6.14 Register Description
- 7 Application Schematic and Layout Considerations
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
SLAVE
SELECT
MISO
MOSI
DATA
CLK
WRITE
ADDRESS BYTE
READ DATA
BYTE 1
READ DATA
BYTE n
DON’T CARE
No Data Transitions (All High or Low) No Data Transitions (All High or Low)
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
b0MISO
MOSI
DATA
CLK
WRITE
MOSI Transitions on Data Clock
Rising Edge
MOSI Valid on Data Clock Falling Edge
t
STE,LEAD
b7
t
LO/HI
t
LO/HI
b6…b1 b0
t
SU,SI
t
HD,SI
1/f
UCxCLK
t
STE,DIS
b6...b1
t
VALID,SO
t
STE,LAG
t
HD,SO
DON’T CARE
READ
Data Transition is on Data Clock
Rising Edge
MISO Valid on Data Clock Falling Edge
t
SU,SO
b7
NO DATA TRANSITIONS
(ALL HIGH/LOW)
Slave
Select
TRF7970A
www.ti.com
SLOS743K –AUGUST 2011–REVISED APRIL 2014
6.10.5.1 Serial Interface Mode With Slave Select (SS)
The serial interface is in reset while the Slave Select signal is high. Serial data in (MOSI) changes on the
rising edge, and is validated in the reader on the falling edge, as shown in Figure 6-19. Communication is
terminated when the Slave Select signal goes high.
All words must be 8 bits long with the MSB transmitted first.
Figure 6-19. SPI With Slave Select Timing Diagram
The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data
changes on the rising edge, and is validated in the reader on the falling edge, as shown in Figure 6-19.
During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is
validated at the eighth falling edge of SCLK, valid data can be read on the MISO pin at the falling edge of
SCLK. It takes eight clock edges to read out the full byte (MSB first). See Section 5.3 for electrical
specifications related to Figure 6-19.
The continuous read operation is shown in Figure 6-20.
Figure 6-20. Continuous Read Operation Using SPI With Slave Select
Copyright © 2011–2014, Texas Instruments Incorporated Detailed Description 39
Submit Documentation Feedback
Product Folder Links: TRF7970A