User's Manual
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Characteristics
- 4 Terminal Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 6.1 Overview
- 6.2 System Block Diagram
- 6.3 Power Supplies
- 6.4 Receiver – Analog Section
- 6.5 Receiver – Digital Section
- 6.6 Oscillator Section
- 6.7 Transmitter – Analog Section
- 6.8 Transmitter – Digital Section
- 6.9 Transmitter – External Power Amplifier and Subcarrier Detector
- 6.10 TRF7970A IC Communication Interface
- 6.11 Special Direct Mode for Improved MIFARE Compatibility
- 6.12 NFC Modes
- 6.13 Direct Commands from MCU to Reader
- 6.13.1 Command Codes
- 6.13.1.1 Idle (0x00)
- 6.13.1.2 Software Initialization (0x03)
- 6.13.1.3 Initial RF Collision Avoidance (0x04)
- 6.13.1.4 Response RF Collision Avoidance (0x05)
- 6.13.1.5 Response RF Collision Avoidance (0x06, n = 0)
- 6.13.1.6 Reset (0x0F)
- 6.13.1.7 Transmission With CRC (0x11)
- 6.13.1.8 Transmission Without CRC (0x10)
- 6.13.1.9 Delayed Transmission With CRC (0x13)
- 6.13.1.10 Delayed Transmission Without CRC (0x12)
- 6.13.1.11 Transmit Next Time Slot (0x14)
- 6.13.1.12 Block Receiver (0x16)
- 6.13.1.13 Enable Receiver (0x17)
- 6.13.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
- 6.13.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
- 6.13.1.16 Receiver Gain Adjust (0x1A)
- 6.13.1 Command Codes
- 6.14 Register Description
- 7 Application Schematic and Layout Considerations
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
Read Data
in
IRQ Status
Register
Dummy Read
Write
Address
Byte
(0x6C)
No Data Transitions (All High or Low)
Don’t Care
Ignore
B7 B6 B5 B4 B3 B2 B1 B0
SLAVE
SELECT
MISO
MOSI
DATA _CLK
No Data Transitions (All High or Low)
B7 B6 B5 B4 B3 B2 B1 B0
TRF7970A
SLOS743K –AUGUST 2011–REVISED APRIL 2014
www.ti.com
The procedure for a dummy read is as follows:
1. Start the dummy read:
(a) When using slave select (SS): set SS bit low.
(b) When not using SS: start condition is when Data Clock is high (see Table 6-10).
2. Send address word to IRQ status register (0x0C) with read and continuous address mode bits set to 1
(see Table 6-10).
3. Read 1 byte (8 bits) from IRQ status register (0x0C).
4. Dummy-read 1 byte from register 0x0D (collision position and interrupt mask).
5. Stop the dummy read:
(a) When using slave select (SS): set SS bit high.
(b) When not using SS: stop condition when Data Clock is high.
Figure 6-17. Procedure for Dummy Read
Figure 6-18. Example of Dummy Read Using SPI With SS
38 Detailed Description Copyright © 2011–2014, Texas Instruments Incorporated
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