User's Manual

Table Of Contents

TRF7970A

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SLOS743K –AUGUST 2011–REVISED APRIL 2014

During transmission, the MCU loads the TRF7970A IC's FIFO (or during reception the MCU removes data

from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile,

the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if

the number of bytes in the FIFO is less than 32 or greater than 96, so that MCU can send new data or

remove the data as necessary. The MCU also checks the number of data bytes to be sent, so as to not

surpass the value defined in TX length bytes. The MCU also signals the transmit logic when the last byte

of data is sent or was removed from the FIFO during reception. Transmission starts automatically after the

first byte is written into FIFO.

Figure 6-13. Example of Checking the FIFO Status Register Using SPI With SS

6.10.2 Parallel Interface Mode

In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high.

This is used to reset the interface logic. Figure 6-14 shows the sequence of the data, with an 8-bit address

word first, followed by data.

Communication is ended by:

• The StopSmpl condition, where a falling edge on the I/O_7 pin is expected while CLK is high.

• The StopCont condition, where the I/O_7 pin must have a successive rising and falling edge while CLK

is low to reset the parallel interface and be ready for the new communication sequence.

• The StopSmpl condition is also used to terminate the direct mode.

Figure 6-14. Parallel Interface Communication With Simple Stop Condition (StopSmpl)

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