User's Manual
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Characteristics
- 4 Terminal Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 6.1 Overview
- 6.2 System Block Diagram
- 6.3 Power Supplies
- 6.4 Receiver – Analog Section
- 6.5 Receiver – Digital Section
- 6.6 Oscillator Section
- 6.7 Transmitter – Analog Section
- 6.8 Transmitter – Digital Section
- 6.9 Transmitter – External Power Amplifier and Subcarrier Detector
- 6.10 TRF7970A IC Communication Interface
- 6.11 Special Direct Mode for Improved MIFARE Compatibility
- 6.12 NFC Modes
- 6.13 Direct Commands from MCU to Reader
- 6.13.1 Command Codes
- 6.13.1.1 Idle (0x00)
- 6.13.1.2 Software Initialization (0x03)
- 6.13.1.3 Initial RF Collision Avoidance (0x04)
- 6.13.1.4 Response RF Collision Avoidance (0x05)
- 6.13.1.5 Response RF Collision Avoidance (0x06, n = 0)
- 6.13.1.6 Reset (0x0F)
- 6.13.1.7 Transmission With CRC (0x11)
- 6.13.1.8 Transmission Without CRC (0x10)
- 6.13.1.9 Delayed Transmission With CRC (0x13)
- 6.13.1.10 Delayed Transmission Without CRC (0x12)
- 6.13.1.11 Transmit Next Time Slot (0x14)
- 6.13.1.12 Block Receiver (0x16)
- 6.13.1.13 Enable Receiver (0x17)
- 6.13.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
- 6.13.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
- 6.13.1.16 Receiver Gain Adjust (0x1A)
- 6.13.1 Command Codes
- 6.14 Register Description
- 7 Application Schematic and Layout Considerations
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
TRF7970A
www.ti.com
SLOS743K –AUGUST 2011–REVISED APRIL 2014
6.3.3 Power Modes
The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits
in the chip status control register (0x00) (see Table 6-3 and Table 6-4).
Table 6-3. 3.3-V Operation Power Modes
(1)
Chip
Regulator Typical
Status SYS_CLK Typical
Control SYS_CLK Power
Mode EN2 EN Control Transmitter Receiver (13.56 V
DD_X
Current
Register (60 kHz) Out
Register MHz) (mA)
(0x0B) (dBm)
(0x00)
Power Down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 -
Sleep Mode 1 0 XX XX OFF OFF OFF ON ON 0.120 -
Standby Mode at
X 1 80 00 OFF OFF ON X ON 2 -
+3.3 VDC
Mode 1 at +3.3 VDC X 1 00 00 OFF OFF ON X ON 3 -
Mode 2 at +3.3 VDC X 1 02 00 OFF ON ON X ON 9 -
Mode 3 (Half Power) at
X 1 30 07 ON ON ON X ON 53 14.5
+3.3 VDC
Mode 4 (Full Power) at
X 1 20 07 ON ON ON X ON 67 17
+3.3 VDC
(1) X = Don't care
Table 6-4. 5-V Operation Power Modes
(1)
Chip
Regulator Typical
Status SYS_CLK Typical
Control SYS_CLK Power
Mode EN2 EN Control Transmitter Receiver (13.56 V
DD_X
Current
Register (60 kHz) Out
Register MHz) (mA)
(0x0B) (dBm)
(0x00)
Power Down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 -
Sleep Mode 1 0 XX XX OFF OFF OFF ON ON 0.120 -
Standby Mode at
X 1 81 07 OFF OFF ON X ON 3 -
+5 VDC
Mode 1 at +5 VDC X 1 01 07 OFF OFF ON X ON 5 -
Mode 2 at +5 VDC X 1 03 07 OFF ON ON X ON 10.5 -
Mode 3 (Half Power) at
X 1 31 07 ON ON ON X ON 70 20
+5 VDC
Mode 4 (Full Power) at
X 1 21 07 ON ON ON X ON 130 23
+5 VDC
(1) X = Don't care
Table 6-3 and Table 6-4 show the configuration for the different power modes when using a 3.3-V or 5-V
system supply, respectively. The main reader enable signal is pin EN. When EN is set high, all of the
reader regulators are enabled, the 13.56-MHz oscillator is running and the SYS_CLK (output clock for
external micro controller) is also available.
The input pin EN2 has two functions:
• A direct connection from EN2 to V
IN
to ensure the availability of the regulated supply V
DD_X
and an
auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is
intended for systems in which the MCU is also being supplied by the reader supply regulator (V
DD_X
)
and the MCU clock is supplied by the SYS_CLK output of the reader. This allows the MCU supply and
clock to be available during sleep mode.
• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this
case the EN input is being controlled by the MCU (or other system device) that is without supply
voltage during complete power down (thus unable to control the EN input). A rising edge applied to the
EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56-
MHz oscillator (identical to condition EN = 1).
Copyright © 2011–2014, Texas Instruments Incorporated Detailed Description 19
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