User's Manual
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Characteristics
- 4 Terminal Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 6.1 Overview
- 6.2 System Block Diagram
- 6.3 Power Supplies
- 6.4 Receiver – Analog Section
- 6.5 Receiver – Digital Section
- 6.6 Oscillator Section
- 6.7 Transmitter – Analog Section
- 6.8 Transmitter – Digital Section
- 6.9 Transmitter – External Power Amplifier and Subcarrier Detector
- 6.10 TRF7970A IC Communication Interface
- 6.11 Special Direct Mode for Improved MIFARE Compatibility
- 6.12 NFC Modes
- 6.13 Direct Commands from MCU to Reader
- 6.13.1 Command Codes
- 6.13.1.1 Idle (0x00)
- 6.13.1.2 Software Initialization (0x03)
- 6.13.1.3 Initial RF Collision Avoidance (0x04)
- 6.13.1.4 Response RF Collision Avoidance (0x05)
- 6.13.1.5 Response RF Collision Avoidance (0x06, n = 0)
- 6.13.1.6 Reset (0x0F)
- 6.13.1.7 Transmission With CRC (0x11)
- 6.13.1.8 Transmission Without CRC (0x10)
- 6.13.1.9 Delayed Transmission With CRC (0x13)
- 6.13.1.10 Delayed Transmission Without CRC (0x12)
- 6.13.1.11 Transmit Next Time Slot (0x14)
- 6.13.1.12 Block Receiver (0x16)
- 6.13.1.13 Enable Receiver (0x17)
- 6.13.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
- 6.13.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
- 6.13.1.16 Receiver Gain Adjust (0x1A)
- 6.13.1 Command Codes
- 6.14 Register Description
- 7 Application Schematic and Layout Considerations
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
TRF7970A
SLOS743K –AUGUST 2011–REVISED APRIL 2014
www.ti.com
6.3.2 Supply Regulator Settings
The input supply voltage mode of the reader needs to be selected. This is done in the Chip Status Control
register (0x00). Bit 0 in register 0x00 selects between 5-V or 3-V input supply voltage. The default
configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply
voltage is below 4.3 V, the 3-V configuration should be used.
The various regulators can be configured to operate in automatic or manual mode. This is done in the
Regulator and I/O Control register (0x0B) as shown in Table 6-1 and Table 6-2.
Table 6-1. Supply Regulator Setting: 5-V System
Register Option Bits Setting in Regulator Control Register
(1)
Address Comments
B7 B6 B5 B4 B3 B2 B1 B0
(hex)
Automatic Mode (default)
0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference
Manual Mode
0B 0 x x x x 1 1 1 V
DD_RF
= 5 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
0B 0 x x x x 1 1 0 V
DD_RF
= 4.9 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
0B 0 x x x x 1 0 1 V
DD_RF
= 4.8 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
0B 0 x x x x 1 0 0 V
DD_RF
= 4.7 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
0B 0 x x x x 0 1 1 V
DD_RF
= 4.6 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
0B 0 x x x x 0 1 0 V
DD_RF
= 4.5 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
0B 0 x x x x 0 0 1 V
DD_RF
= 4.4 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
0B 0 x x x x 0 0 0 V
DD_RF
= 4.3 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
(1) x = Don't care
Table 6-2. Supply Regulator Setting: 3-V System
Register Option Bits Setting in Regulator Control Register
(1)
Address Comments
B7 B6 B5 B4 B3 B2 B1 B0
(hex)
Automatic Mode (default)
0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference
Manual Mode
0B 0 x x x x 1 1 1 V
DD_RF
= 3.4 V, V
DD_A
= 3.4 V, V
DD_X
= 3.4 V
0B 0 x x x x 1 1 0 V
DD_RF
= 3.3 V, V
DD_A
= 3.3 V, V
DD_X
= 3.3 V
0B 0 x x x x 1 0 1 V
DD_RF
= 3.2 V, V
DD_A
= 3.2 V, V
DD_X
= 3.2 V
0B 0 x x x x 1 0 0 V
DD_RF
= 3.1 V, V
DD_A
= 3.1 V, V
DD_X
= 3.1 V
0B 0 x x x x 0 1 1 V
DD_RF
= 3.0 V, V
DD_A
= 3.0 V, V
DD_X
= 3.0 V
0B 0 x x x x 0 1 0 V
DD_RF
= 2.9 V, V
DD_A
= 2.9 V, V
DD_X
= 2.9 V
0B 0 x x x x 0 0 1 V
DD_RF
= 2.8 V, V
DD_A
= 2.8 V, V
DD_X
= 2.8 V
0B 0 x x x x 0 0 0 V
DD_RF
= 2.7 V, V
DD_A
= 2.7 V, V
DD_X
= 2.7 V
(1) x = Don't care
The regulator configuration function adjusts the regulator outputs by default to 400 mV below V
IN
level, but
not higher than 5 V for V
DD_RF
, 3.4 V for V
DD_A
and V
DD_X
. This ensures the highest possible supply
voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio).
18 Detailed Description Copyright © 2011–2014, Texas Instruments Incorporated
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